Exact Adder Research Articles

Hybrid Radix-4 SESA/SEDA Adders for Medical Image Processing

Adders play a critical role as primary modules in circuit design, supporting error-tolerant applications such as machine learning, digital image processing, and signal processing. Therefore, the development of adders with low power consumption and energy efficiency is of utmost importance. Approximate adders outperform exact adders in VLSI chips. Among approximate adders, the hybridization of Single Exact and Single Approximation (SESA) and Single Exact and Dual Approximation (SEDA) techniques has emerged as a promising solution. These hybrid adders offer superior power and energy savings relative to other accurate and approximate adder designs. In this scheme, we propose the integration of hybrid radix-4 adders with approximation adders to achieve enhanced performance and pave the way for future hybrid approximate adder circuits. Extensive simulations validated the efficacy of the proposed approach. Furthermore, practical applications demonstrated the versatility and potential of hybrid adders in real-world scenarios. The proposed methodology ensures cost-effectiveness and facilitates seamless future updates and extensions. Overall, this research contributes to the advancement of efficient and low-power adder designs, addressing the evolving requirements of modern digital systems.

Low Power Adders for Efficient Image Processing Applications

In the world of digitalization, low-power circuits are necessary for building fast operating processors. Additionally, low-power circuits consume less energy and the lifetime of the electronic devices can extended to the maximum. Adders are significantly used in digital image processing techniques and for many Very Large-Scale Integration (VLSI) applications. Due to this, demand for creating efficient adders has become high in recent years. Using approximate adders is much more convenient than exact adders and the results of approximation adders are better than exact adders. Approximation adders can be executed for many signal-processing applications and are mainly considered for image-processing applications. SESA and SEDA are very good in providing efficiently lower energy when compared to other mirror adder circuits and are cost-efficient. Improvements and further extensions of the proposed model can easily make for building efficient microprocessor chips and these adders are used in next-generation electronic devices.

Energy-Efficient Hardware Implementation of Fully Connected Artificial Neural Networks Using Approximate Arithmetic Blocks.

In this paper, we explore efficient hardware implementation of feedforward artificial neural networks (ANNs) using approximate adders and multipliers. Due to a large area requirement in a parallel architecture, the ANNs are implemented under the time-multiplexed architecture where computing resources are re-used in the multiply accumulate (MAC) blocks. The efficient hardware implementation of ANNs is realized by replacing the exact adders and multipliers in the MAC blocks by the approximate ones taking into account the hardware accuracy. Additionally, an algorithm to determine the approximate level of multipliers and adders due to the expected accuracy is proposed. As an application, the MNIST and SVHN databases are considered. To examine the efficiency of the proposed method, various architectures and structures of ANNs are realized. Experimental results show that the ANNs designed using the proposed approximate multiplier have a smaller area and consume less energy than those designed using previously proposed prominent approximate multipliers. It is also observed that the use of both approximate adders and multipliers yields, respectively, up to 50% and 10% reduction in energy consumption and area of the ANN design with a small deviation or better hardware accuracy when compared to the exact adders and multipliers.

Accuracy Configurable Adders with Negligible Delay Overhead in Exact Operating Mode

In this paper, two accuracy configurable adders capable of operating in approximate and exact modes are proposed. In the adders, which include a block-based carry propagate and a parallel prefix structure, the carry chains are cut off in the approximate mode limiting the carry chain depth to two blocks. In the case of parallel prefix adder, we propose a special carry generate tree equipped with a power gating means. In both of the proposed structures, the critical paths of the adders are not increased in the exact operating mode. Thus, the main objective of proposing these approximate adder structures is to present an accuracy configurable adder structure whose delay in the exact mode is almost the same as an exact adder. The efficacies of the proposed accuracy configurable adders are compared with some state-of-the-art adder structures using a 15nm CMOS technology. In addition, their efficacies are evaluated in two error-resilient applications. These studies show that the proposed carry-propagate adder has 22% (51%) lower energy consumption (error rate) compared to the best prior works. Also, the proposed parallel prefix adder provides, on average, 20% lower energy consumption compared to the exact parallel prefix adders.

BEAD: Bounded error approximate adder with carry and sum speculations

This paper proposes a configurable reduced worst-case error approximate adder, named BEAD (Bounded Error Approximate Adder). The proposed adder is based on segmentation and carry speculation methods to cut long critical paths. Furthermore, a high accuracy speculation method is proposed to calculate the sum bits. However, the data of real-world applications is often not uniformly distributed, which leads to taking values that result in a worst-case error of the approximate adder quite frequently; therefore, considerable distortion occurs at the output. To overcome this, the carry prorogation scheme of the BEAD is such that the error distance is bounded to a given value, which makes it more accurate rather than prior works. Specifically, the BEAD offers a smaller worst-case error in addition to improved mean relative error distance. The results show between 50% and 80% smaller maximum error compared to the related works. Also, by synthesizing the different adders using a 15-nm FinFET technology, the results demonstrate that the BEAD has at least 30% area saving compared to the exact adder in the various studied configurations. The proposed adder achieves the almost lowest figure of cost (FoC) compared to state-of-the-art approximate adders. Moreover, BEAD's evaluation in image processing and DCT applications shows its great superiority over recently proposed structures.

Bitwise Logical Operations in VCMA-MRAM

Today’s technology demands compact, portable, fast, and energy-efficient devices. One approach to making energy-efficient devices is an in-memory computation that addresses the memory bottleneck issues of the present computing system by utilizing a spintronic device viz. magnetic tunnel junction (MTJ). Further, area and energy can be reduced through approximate computation. We present a circuit design based on the logic-in-memory computing paradigm on voltage-controlled magnetic anisotropy magnetoresistive random access memory (VCMA-MRAM). During the computation, multiple bit cells within the memory array are selected that are in parallel by activating multiple word lines. The designed circuit performs all logic operations-Read/NOT, AND/NAND, OR/NOR, and arithmetic SUM operation (1-bit approximate adder with 75% accuracy for SUM and accurate carry out) by slight modification using control signals. All the simulations have been performed at a 45 nm CMOS technology node with VCMA-MTJ compact model by using the HSPICE simulator. Simulation results show that the proposed circuit’s approximate adder consumes about 300% less energy and 2.3 times faster than its counterpart exact adder.

A Double Bit Approximate Adder Providing a New Design Perspective for Gate-Level Design

In the modern Block-chain and Artificial Intelligence era, energy efficiency has become one of the most important design concerns. Approximate computing is a new and an evolving field promising to provide energy-accuracy trade-off. Several applications are tolerant to small degradation in results, and hence tasks like image and video processing are candidates to benefit from Approximate Computing. In this paper, we propose a new design approach for designing approximate adders and further optimize the accuracy and cost metrics. Our approach is based on minimizing the errors while cascading more than one 1-bit adder. We insert [Formula: see text] on specific locations to achieve a reasonable circuit minimization and reduce the [Formula: see text] cost. We compare our design with exact adder and relevant state-of-the-art approximate adders. Through analysis and simulations, we show that our approach provides higher accuracy and far better performance compared with other designs. The proposed double bit approximate adder provides more than 25% savings in gate count compared with the exact adder, has a mean absolute error of 0.25 which is lowest among all the reference approximate adders and reduces the power-delay product by more than 60% compared to the exact adder. When employed for image filtering, the proposed design provides a [Formula: see text] of 96%, a [Formula: see text] of 95% and a [Formula: see text] of 91% relative to the actual results, while the second best approximate adder only achieves 64%, 54% and 71% of these image quality metrics, respectively.

Significance-Driven Logic Compression for Energy Efficient Multiplier Design

Approximate Arithmetic is a new design paradigm that is being used in many applications which are tolerant to imprecision and do not require accurate results. It can reduce circuit complexity, delay and energy consumption by relaxing accuracy requirements. The partial product bit matrix can be reduced based on their progressive bit significance using a Significance Driven Logic Compression(SDLC) approach. Further, the complexity of the approximate multiplier can be reduced by using Approximate adders in place of exact adders in the accumulation method. Removing some of the transistors from an accurate adder will result in an approximate adder. By using approximate adders which have less number of transistors, the power, propagation delay, and the switching capacitance can be reduced. In this paper, approximate multipliers are implemented using different approximate adders and they are compared with an exact multiplier in terms of power, delay and energy savings.

Design of Approximate Circuits by Fabrication of False Timing Paths: The Carry Cut-Back Adder

This paper introduces a novel method for designing approximate circuits by fabricating and exploiting false timing paths, i.e., critical paths that cannot be logically activated. This allows to strongly relax timing constraints while guaranteeing minimal and controlled behavioral change. This technique is applied to an approximate adder architecture, called the Carry Cut-Back Adder (CCBA), in which high-significance stages can cut the carry propagation chain at lower-significance positions. This lightweight approach prevents the logic activation of the carry chain, improving performance and energy efficiency while guaranteeing low worst-case errors. A design methodology is presented along with implementation, error optimization, and design-space minimization. The CCBA is proven capable of extremely high accuracy while displaying significant circuit savings. For a worst case precision of 99.999%, energy savings up to 36% are demonstrated compared with exact adders. Finally, an industry-oriented comparison of 32-bit approximate and truncated adders is carried out for mean and worst-case relative errors. The CCBA outperforms both state-of-the-art and truncated adders for high-accuracy and low-power circuits, confirming the interest of the proposed concept to help building highly-efficient approximate or precision-scalable hardware accelerators.

A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons.

Human intelligence relies on the vast number of neurons and their interconnections that form a parallel computing engine. If we tend to design a brain-like machine, we will have no choice but to employ many spiking neurons, each one has a large number of synapses. Such a neuronal network is not only compute-intensive but also memory-intensive. The performance and the configurability of the modern FPGAs make them suitable hardware solutions to deal with these challenges. This paper presents a scalable architecture to simulate a randomly connected network of Hodgkin-Huxley neurons. To demonstrate that our architecture eliminates the need to use a high-end device, we employ the XC7A200T, a member of the mid-range Xilinx Artix®-7 family, as our target device. A set of techniques are proposed to reduce the memory usage and computational requirements. Here we introduce a multi-core architecture in which each core can update the states of a group of neurons stored in its corresponding memory bank. The proposed system uses a novel method to generate the connectivity vectors on the fly instead of storing them in a huge memory. This technique is based on a cyclic permutation of a single prestored connectivity vector per core. Moreover, to reduce both the resource usage and the computational latency even more, a novel approximate two-level counter is introduced to count the number of the spikes at the synapse for the sparse network. The first level is a low cost saturated counter implemented on FPGA lookup tables that reduces the number of inputs to the second level exact adder tree. It, therefore, results in much lower hardware cost for the counter circuit. These techniques along with pipelining make it possible to have a high-performance, scalable architecture, which could be configured for either a real-time simulation of up to 5120 neurons or a large-scale simulation of up to 65536 neurons in an appropriate execution time on a cost-optimized FPGA.