A Scalable FPGA Architecture for Randomly Connected Networks of Hodgkin-Huxley Neurons.

Kaveh Akbarzadeh-Sherbaf,Behrooz Abdoli,Abdol-Hossein Vahabie,Saeed Safari

doi:10.3389/fnins.2018.00698

Kaveh Akbarzadeh-Sherbaf, Behrooz Abdoli + Show 2 more

Open Access

https://doi.org/10.3389/fnins.2018.00698

Copy DOI

Abstract

Human intelligence relies on the vast number of neurons and their interconnections that form a parallel computing engine. If we tend to design a brain-like machine, we will have no choice but to employ many spiking neurons, each one has a large number of synapses. Such a neuronal network is not only compute-intensive but also memory-intensive. The performance and the configurability of the modern FPGAs make them suitable hardware solutions to deal with these challenges. This paper presents a scalable architecture to simulate a randomly connected network of Hodgkin-Huxley neurons. To demonstrate that our architecture eliminates the need to use a high-end device, we employ the XC7A200T, a member of the mid-range Xilinx Artix®-7 family, as our target device. A set of techniques are proposed to reduce the memory usage and computational requirements. Here we introduce a multi-core architecture in which each core can update the states of a group of neurons stored in its corresponding memory bank. The proposed system uses a novel method to generate the connectivity vectors on the fly instead of storing them in a huge memory. This technique is based on a cyclic permutation of a single prestored connectivity vector per core. Moreover, to reduce both the resource usage and the computational latency even more, a novel approximate two-level counter is introduced to count the number of the spikes at the synapse for the sparse network. The first level is a low cost saturated counter implemented on FPGA lookup tables that reduces the number of inputs to the second level exact adder tree. It, therefore, results in much lower hardware cost for the counter circuit. These techniques along with pipelining make it possible to have a high-performance, scalable architecture, which could be configured for either a real-time simulation of up to 5120 neurons or a large-scale simulation of up to 65536 neurons in an appropriate execution time on a cost-optimized FPGA.

Highlights

Computational neuroscientists and computer researchers have two complementary views on mathematical modeling of the human intelligence
Implementing exponential functions is costly from the logic resources point of view; we look for approximate methods with lower cost
To demonstrate the capabilities of our proposed architecture, we use Verilog hardware description language to describe the example explained in section 2.6; that is, a network made of 4 cores and 4096 neurons

Summary

Introduction

Computational neuroscientists and computer researchers have two complementary views on mathematical modeling of the human intelligence. NEURON (Carnevale and Hines, 2006), GENESIS (Kornbaum and Enderle, 1995), NEST (Gewaltig and Diesmann, 2007), Brian (Goodman and Brette, 2009), NeMo (Fidjeland et al, 2009), PCSIM (Pecevski, 2009), PyNN (Davison, 2009), and HRLSim (Minkovich et al, 2014) are of the most cited ones All of these frameworks today support GPUs to speed up simulations (Brette et al, 2007), their hardwired microarchitectures put obstacles in the way of parallelism utilization for irregular applications such as spiking neural networks (Fung, 2015). A custom hardware design using either ASIC or FPGA is an alternative way that is more amenable to parallelism

Objectives

Methods

Results