Current Multiplier Based Synapse and Neuron Circuits for Compact SNN Chip

Abstract

Spiking Neural Networks having biological plausible architecture are considered to be more suitable for energy efficient hardware implementation. When it comes to realize the hardware implementation of a large-scale Neural network for mobile applications, area and power consumption constraints become more critical. Optimizing Spiking neural network, constituting of neuron and synapse circuits, for area and power is essential. In this paper we present a more optimized version of Synapse and neuron circuits. We propose an analog CMOS implementation of a current multiplier charge injector-based Synapse and neuron circuit. The synapse circuit modulates the input spike rates by a trained weight value and injects an equivalent current. The neuron circuit integrates the injected synaptic current and evokes an output digital spike event. The circuit implementation is done using 65nm process design kit. The proposed circuit implementation exhibits all the temporal characteristics of Spiking neural networks. The circuit implementation has been optimized for area and power consumption and therefore can be easily constituted into a large-scale spiking neural network. Furthermore, the compact circuit implementation can benefit from the high resolution with very less increase in area and power.