Testing Of Programmable Analog Neural Network Processors

Abstract

Artificial neural networks are capable of high-speed com- putation to solve many complex problems in scientific and engineering applications. A systematic method to test large arrays of analog, digital, or mixcd-signal circuit components that constitute these networks is describcd. The testing procedure consists of a parametric test and a behavioral test. Characteris- tics of the input neuron, synapse, and output neuron circuits are used to distinguish between faulty and useful chips. Several measurement results from neural network chips are presented to demonstrate the testing procedure. into the current mirror which is used to bias the synapse circuit. The synapsc is fully programmable, with the analog weight being stored on a DRAM-style capacitor which is addressed by using row and column decoders. The synapse circuit is a transconduc- tance amplifier. The synapse weight voltage, Vprog, determines the synapse output current, Id. The summed synapse output current drives the output neuron circuit. The output neuron is a two-stage operational amplificr with adjustable gain. The gain control is achieved by changing the bias of an NMOS transistor that is connected in the feedback loop of the amplifier. The schematic of a different implementation of input neuron, synapse and output neuron circuits is shown in Fig. 4. The input ncuron consists of an operational amplifier connected as a unity- gain buffer. The synapse circuit is made up of a modified Gilbert multiplier (lo) with low lincarity error over a wide dynamic range. The synapse weight is stored in a differential format in order to improve the accuracy of the weighted multiplication operation. In the output neuron, currents from the synapses that are connected to it are summcd and hen converted into a voltage by an I-V con- verter circuit. The output neuron also contains buffers with active feedback resistors in order to implement a sigmoid function with a controllable voltage gain. A winncr-take-all circuit is used to select the largest output when a self-organizing neural network chip is designed.