Significance-Driven Logic Compression for Energy Efficient Multiplier Design

Abstract

Approximate Arithmetic is a new design paradigm that is being used in many applications which are tolerant to imprecision and do not require accurate results. It can reduce circuit complexity, delay and energy consumption by relaxing accuracy requirements. The partial product bit matrix can be reduced based on their progressive bit significance using a Significance Driven Logic Compression(SDLC) approach. Further, the complexity of the approximate multiplier can be reduced by using Approximate adders in place of exact adders in the accumulation method. Removing some of the transistors from an accurate adder will result in an approximate adder. By using approximate adders which have less number of transistors, the power, propagation delay, and the switching capacitance can be reduced. In this paper, approximate multipliers are implemented using different approximate adders and they are compared with an exact multiplier in terms of power, delay and energy savings.