Etching Damage Research Articles

Improvement of electrical performance using PtSe2/PtTe2 edge contact synthesized by molecular beam epitaxy

One-dimensional (1D) edge contact is considered critical to reducing contact resistance between two-dimensional transition-metal dichalcogenides (TMDs) and contact metal and overcoming surface contact effects, such as surface damage and orbital hybridization. Although several studies have investigated edge contact, some problems such as inevitable etching damage and a limited area persist. Herein, a tellurization method is applied to a specific lateral region to fabricate PtTe2/PtSe2/PtTe2 edge-contact field-effect transistors (FETs) without etching damage. High-resolution X-ray photoelectron spectroscopy and Raman spectroscopy are used to verify tellurization completion, which is evidenced by the complete transformation of PtSe2 to PtTe2 by the substitution of Se atoms with evaporated Te atoms. Furthermore, tellurization is applied to a specific lateral region by utilizing the hexagonal boron nitride to block the interdiffusion of evaporated Te atoms, which is confirmed by Raman spectroscopy and cross-sectional annular dark-field scanning transmission electron microscopy. Finally, the 1D edge-contact FETs fabricated by tellurization demonstrate a higher on–off ratio and carrier mobility than the surface-contact FET. Therefore, this method can be applied to various FETs based on TMDs for improving electrical performance through a reduction in contact resistance.

Influence of the carrier wafer during GaN etching in Cl2 plasma

In this study, we have performed a thorough characterization of the GaN surface after etching up to 100 nm in Cl2 plasma under various bias voltages and according to the carrier wafer used (Si, SiO2, Si3N4, and photoresist). The objective of this article is to evaluate the etch damage and contamination of the GaN surface when materials with other chemical nature are present during etching. The effects of etching conditions on surface morphology and chemical compositions of etched GaN films are studied in detail using XPS and AFM measurements. To this aim, a universal methodology is proposed to estimate accurately by XPS the stoichiometry of the GaN surface exposed to reactive plasmas when only an Al Kα x-ray source is available. The results indicate that the GaN etching mechanisms are very sensitive to the chlorine radical density present in the plasma, the latter being strongly influenced by the carrier wafer. Substrates that are more chemically reactive with Cl2 plasma such as silicon or photoresist compared to SiO2 or Si3N4 will lead to a greater loading of atomic chlorine, which in turn will lead to lower GaN etch rates. Moreover, the GaN surface contamination will depend on the etch by-products ejected by the carrier wafer. The GaN surface exposed to Cl2 plasma shows a Ga-depleted surface because of the more important reactivity of Cl with Ga rather than N, except in the SiO2 carrier wafer case. In this latter case, the formation of Ga–O bond limits the Ga removal. Regarding the surface roughness, it seems that the contaminants play a little role in the roughness formation except for the oxygen released by the SiO2 carrier wafer. On the other hand, the surface roughness evolution is clearly driven by the chlorine radical flux reaching the GaN surface. At low bias voltage, a preferential crystalline orientation etching driven by the Cl radicals leads to the formation of hexagonal shaped defects that are associated to screw-type threading dislocations already present in the pristine GaN material. At higher bias, the enlargement of the defects is limited, leading to a very low surface roughness value but to amorphized surfaces.

Wide-range-adjusted threshold voltages for E-mode AlGaN/GaN HEMT with a p-SnO cap gate

p-GaN cap layer has been recognized as a commercial technology to manufacture enhanced-mode (E-mode) AlGaN/GaN high electron mobility transistor (HEMT); however, the difficult activation of Mg doping and etching damage of p-GaN limit the further improvement of device performance. Thus, the more cost-effective cap layer has attracted wide attention in GaN-based HEMT. In this paper, p-type tin monoxide (p-SnO) was firstly investigated as a gate cap to realize E-mode AlGaN/GaN HEMT by both Silvaco simulation and experiment. Simulation results show that by simply adjusting the thickness (50 to 200 nm) or the doping concentration (3 × 1017 to 3 × 1018 cm−3) of p-SnO, the threshold voltage (Vth) of HEMT can be continuously adjusted in the range from zero to 10 V. Simultaneously, the device demonstrated a drain current density above 120 mA mm−1, a gate breakdown voltage (VBG) of 7.5 V and a device breakdown voltage (VB) of 2470 V. What is more, the etching-free AlGaN/GaN HEMT with sputtered p-SnO gate cap were fabricated, and achieved a positive Vth of 1 V, VBG of 4.2 V and VB of 420 V, which confirms the application potential of the p-SnO film as a gate cap layer for E-mode GaN-based HEMT. This work is instructive to the design and manufacture of p-oxide gate cap E-mode AlGaN/GaN HEMT with low cost.

Ohmic contact on low-doping-density p-type GaN with nitrogen-annealed Mg

We have demonstrated a fabrication process for the Ohmic contact on low-doping-density p-type GaN with nitrogen-annealed Mg. An Ohmic contact with a contact resistance of 0.158 Ω cm2 is realized on p−-GaN ([Mg] = 1.3 × 1017 cm−3). The contact resistance of p-type GaN with higher Mg concentration ([Mg]=1.0 × 1019 cm−3) can also be reduced to 2.8 × 10−5 Ω cm2. A localized contact layer is realized without any etching or regrowth damage. The mechanism underlying this reduced contact resistance is studied by scanning transmission electron microscopy with energy dispersive x-ray spectroscopy and secondary ion mass spectrometry, representing a mutual diffusion of Ga and Mg atoms on the interface. Reductions in the barrier height and surface depletion width with the nitrogen-annealed Mg layer are confirmed by XPS and Hall effect measurements qualitatively.

Effect of post anode annealing on W/Au and Ni/Au multi-channel AlGaN/GaN Schottky diode

In this paper, multi-channel AlGaN/GaN Schottky diodes (MC-SBDs) with W/Au and Ni/Au anode metal were fabricated on the Si substrates, and the effect of post anode annealing (PAA) was investigated. The temperature of PAA varies from 300 °C to 550 °C. Benefitting from the multi-channel structure, low on-resistance ( R ON ) of 3.11 Ω mm are obtained for Ni and W after 300 °C PAA. Meanwhile, the onset voltage ( V ON ) of W is 0.34 V, much lower than 0.71 V for Ni. With PAA temperature rising, the V ON and barrier height ( φ b ) increase for both metals at the beginning because of the repair of etching damage. However, these parameters will decrease when the temperature exceeds the optimal value due to the deterioration of the Schottky interface. Correspondingly, the reverse current ( I REV ) drops first and then rises. The optimal PAA temperature is 450 °C for Ni and 500 °C for W. Furthermore, the temperature-dependent characteristics are also measured for comprehensive evaluation. The results show that the PAA has little effect on temperature-dependent forward characteristics for both Ni and W. However, the PAA can improve the high-temperature stability of I REV for Ni, whereas this advantage has not been observed on W, which is related to different leakage current mechanisms. • Successfully fabricated multi-channel AlGaN/GaN Schottky diodes on Si substrate. • Comparison of the device characteristics of W and Ni as anode metal. • Study on different post anode annealing temperatures. • Temperature-dependent I–V characteristics after post anode annealing.

72 nm Pitch Hexagonal MTJ Array on DRAM Platform for High-Density MRAM

Well isolated 72 nm pitch hexagonal honeycomb magnetic tunneling junction (MTJ) array with about 45 nm MgO CD was successfully fabricated on a DRAM platform by using mature DRAM array patterning solution with self-aligned double patterning technology and proposed triple hard mask scheme. The 72 nm pitch MTJ array had an equivalent cell size as small as <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.0044~\mu \text{m}$ </tex-math></inline-formula> <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , the world’s smallest pitch size and cell size for industrial MTJ array to our knowledge. The hexagonal array geometry offered considerably merit for storage density enhancement and MTJ etch convenience. A reactive ion etch (RIE) and ion beam etch (IBE) combined MTJ etching solution was adopted to optimize pillar isolation and mitigate metallic re-deposition and etch damage. Perpendicular magnetic anisotropy was maintained in MTJ array; however, free layer coercivity was smaller than expected, indicating the existence of etch damage or fringe magnetic field interaction. Potential challenges for the chip integration of high-density hexagonal MTJ array are also discussed.

(Invited) Recent Progress on Selective Area Regrowth and Doping for Vertical GaN Power Transistors

Wide bandgap semiconductor GaN is a very promising candidate for efficient power conversion applications due to its large bandgap energy and high critical electric field. Vertical GaN power devices grown on bulk substrates are enabling the next-generation power electronics with higher efficiency, higher power density and smaller form factor. However, selective area doping in GaN is far from mature, which is limiting the realization of many advanced GaN power devices such as vertical junction effect transistors (VJFETs), junction barrier Schottky (JBS), superjunction, and junction termination extension (JTE). Epitaxial regrowth or selective area regrowth has been regarded as one of the most promising routes to selective area doping.Currently, the regrown p-n junctions suffer from large leakage currents and premature breakdown. To understand this phenomena, the regrowth experiments were carried out by metalorganic chemical vapor deposition via an etching-then-regrowth process. The etching was performed by inductively coupled plasma (ICP) etching. The regrowth dynamics with different trench widths and depths was revealed, where basal plane and lateral growth modes were identified. It was also found that shallow trenches for selective area regrowth was beneficial for reducing the reverse leakage currents of regrown p-n junctions.The regrowth interface plays a critical role in understating the leakage mechanism of regrown p-n junctions. With developed material characterization techniques, the regrown structures and interface were analyzed in detail. Cathodoluminescence (CL) and secondary electrons (SEs) were used to realize both lateral and vertical dopant profiling at a sub-micron scale [1]. The regrowth interface by dry etching accumulated lots of impurities and charges, contributing to the formation of a p+-n+ tunneling junction. This was further confirmed by the electrostatic potential profile at the regrowth interface using electron holography [2]. This tunneling junction is likely to be the major contributor to the large reverse leakage currents and low breakdown voltages in regrown junctions. To improve the regrowth interface, novel etching technologies were demonstrated. It was found that low-power dry etching significantly reduced the interfacial charges and the reverse leakage currents of regrown p-n junctions [3]. Atomic layer etching (ALE) was also successfully developed for GaN, which uses self-limiting chemical processes, thus removing the damaged layers without inducing further etching damage. The tertiarybutylchloride (TBCl) based in situ etching may serve as an alternative etching method to dry etching with reduced etching damage [4]. In terms of devices, regrown p-n junctions with low leakage currents [3] and the first normally-off VJFETs were demonstrated. Further improvements in selective area regrowth and associated devices can be expected via regrowth optimization and regrowth interface engineering via surface treatments and low-damage etching. These results represent an important step towards realizing selective area doping for GaN power transistors. H. Liu et al., Appl. Phys. Lett., 114, 082102 (2019)S. Alugubelli, et al., Appl. Phys. Lett., 115, 201602 (2019)K. Fu et al., IEEE Electron Device Lett. 40, 1728 (2019)B. Li et al., Appl. Phys. Lett., 115, 162101 (2019)

Radical flux control in reactive ion beam etching (RIBE) by dual exhaust system

Radicals generated during reactive ion etching (RIE) cannot be electrically controlled, causing isotropic etching and chemical damage to the sidewall of the etched feature during the etching process. In this study, using a reactive ion beam etcher (RIBE) installed with a dual exhaust system, where an additional exhaust valve was introduced to pump out radicals from the inductively coupled plasma (ICP) source chamber in addition to the conventional main gate valve in the process chamber, the radical flux relative to ion flux during the RIE process has been controlled and the effect of additional exhausting through the ICP source chamber for the control of radical flux relative to ion flux on the properties of etching has been investigated using CF4 gas. The results showed that the additional exhausting of the radicals through the ICP source chamber not only decreased the ICP source chamber pressure but also decreased the ratio of radical flux to ion flux to the substrate. The lower ICP source chamber pressure could be also obtained without additional exhausting through the ICP source chamber by decreasing the CF4 gas flow rate to the ICP source chamber, however, the lower ratio of radical flux to ion flux was observed for the dual exhaust system. It is believed that, for the next generation RIBE, multiple exhausting is beneficial for anisotropic etching of nanoscale features by controlling the radical flux to the sidewall and ion flux to the bottom of a nanoscale feature during the etching.

Effects of Seed-Layer N2O Plasma Treatment on ZnO Nanorod Based Ultraviolet Photodetectors: Experimental Investigation with Two Different Device Structures.

The crystalline quality of ZnO NR (nanorod) as a sensing material for visible blind ultraviolet PDs (photodetectors) critically depends on the SL (seed layer) material of properties, which is a key to high-quality nanocrystallite growth, more so than the synthesis method. In this study, we fabricated two different device structures of a gateless AlGaN/GaN HEMT (high electron mobility transistor) and a photoconductive PD structure with an IDE (interdigitated electrode) pattern implemented on a PET (polyethylene terephthalate) flexible substrate, and investigated the impact on device performance through the SL N2O plasma treatment. In case of HEMT-based PD, the highest current on-off ratio (~7) and spectral responsivity R (~1.5 × 105 A/W) were obtained from the treatment for 6 min, whereas the IDE pattern-based PD showed the best performance (on-off ratio = ~44, R = ~69 A/W) from the treatment for 3 min and above, during which a significant etch damage on PET substrates was produced. This improvement in device performance was due to the enhancement in NR crystalline quality as revealed by our X-ray diffraction, photoluminescence, and microanalysis.

Photonic rocket structure grown by site-selective and bottom-up approach: A directional and Gaussian-like quantum emitter platform

Semiconductor quantum dots (QDs) integrated with photonic nanowires are one of the representative platforms for high-purity single photonic sources. However, conventional photonic nanowires suffer from severe scattering at the edge owing to the small footprint. For this reason, tapered structures have been adopted to achieve directional emission with minimized scattering, and hence, high light collection efficiency. So far, various tapered structures have been demonstrated by using top-down etching fabrication or catalyst-assisted growth. However, these approaches can induce critical issues for QD integrated photonic devices such as an etching damage, an inclusion of multiple QDs in a wire, a misalignment of QD with respect to the wire axis center, or a contamination of QD by the catalyst. Therefore, developing a catalyst-free, site-controlled growth technique is essential for high-quality tapered nanowire structures. In this work, we propose a site-selectively grown photonic rocket structure, which consists of a pencil-like nanowire and a pyramid acting as a single-mode waveguide and a coupler, respectively. Since this structure is defined by stable crystal facets, the dimensions of the structure, especially its tapering angle, are determined precisely. Most significantly, a single QD can be formed at the apex, deterministically aligned to the axis center of the photonic structure. We analyzed the propagating mode inside the photonic nanowire and pyramid coupler using finite-difference time-domain simulations. This photonic rocket structure produces directional emission owing to the pyramid coupler, resulting in 2.9 (2.0) times larger light collection efficiency with a numerical aperture of 0.3 (0.7), compared to the nanowire structure alone.

High power-added-efficiency AlGaN/GaN HEMTs fabricated by atomic level controlled etching

An atomic-level controlled etching (ACE) technology is invstigated for the fabrication of recessed gate AlGaN/GaN high-electron-mobility transistors (HEMTs) with high power added efficiency. We compare the recessed gate HEMTs with conventional etching (CE) based chlorine, Cl2-only ACE and BCl3/Cl2 ACE, respectively. The mixed radicals of BCl3/Cl2 were used as the active reactants in the step of chemical modification. For ensuring precise and controllable etching depth and low etching damage, the kinetic energy of argon ions was accurately controlled. These argon ions were used precisely to remove the chemical modified surface atomic layer. Compared to the HEMTs with CE, the characteristics of devices fabricated by ACE are significantly improved, which benefits from significant reduction of etching damage. For BCl3/Cl2 ACE recessed HEMTs, the load pull test at 17 GHz shows a high power added efficiency (PAE) of 59.8% with an output power density of 1.6 W/mm at V d = 10 V, and a peak PAE of 44.8% with an output power density of 3.2 W/mm at V d = 20 V in a continuous-wave mode.

(Invited) Layer Transfer Technology for Stacked Multi-Channel Semiconductor-on-Insulator Platform

Continuous scaling of device dimension pushed Si channel to its physical limit, alternative high mobility channels such as (Si)Ge and (In)GaAs have been considered to replace Si to further enhance CMOS performance. In the meantime, ultrathin body (UTB) semiconductor-on-insulator is compulsory structure for improved gate control and immunity against short channel effects in the ultimately scaled high performance and low power dissipation CMOS. To realize stacked multi- channel semiconductor-on-insulator platform on current mainstream Si wafers, layer transfer technology [1-3] utilizing direct bonding and selective etching was developed to integrate (Si)Ge or (In)GaAs channels on Si, showing great potential for ultimate device structures with heterogeneous integration.Figure 1(a) is the process flow for integrating InGaAs channel onto SiGe-on-insulator (SGOI) structure utilizing layer transfer technology [4]. It started with bottom SGOI pMOSFET fabrication. The SGOI structure was realized by 2-step Ge condensation technique, resulting in Ge content of 70%. After high k metal gate process, self-aligned Ni-SiGe alloy was formed as S/D metal. Subsequently, SiO2 interlayer was deposited by CVD, followed by CMP planarization. Then, InGaAs grown on InP was directly bonded onto SiO2 and InP substrates were selectively etched away. Finally, the top InGaAsOI nMOSFET fabrication and metal interconnection completed the CMOS fabrication. Fig. 1(b) shows the cross-sectional TEM images of fabricated InGaAs/SiGe channel stacked CMOS. Well aligned top and bottom devices are seen without any distinct defects.Figures 2 is a schematic flow for fabricating Ge/Si double channel-on-insulator structure by low temperature hetero-layer bonding technology (LT-HBT). The technology starts with the preparation of donor wafers (Fig. 2(a)) for the top Ge channel layer and host wafers (Fig. 2(b)) for the bottom Si channel layer. For donor wafers, a 200-nm-thick Ge was epitaxially grown on SOI wafer by reduced pressure CVD. After CMP planarization, ALD SiO2 is deposited onto Ge. For host wafers, implantation and dopant activation were carried out, followed by chemical treatment for Si oxidation. After surface activation by room temperature chemical treatment (Fig. 2(c)), the direct wafer bonding of both SiO2 surface was performed at 200 °C in a press machine (Fig. 2(d)). Then, the Si substrate of the donor wafer was removed with deep RIE. At this time, the BOX layer of the donor wafer serves as an etch-stop layer. Subsequently, the BOX layer and thin Si layer of the donor wafer were removed selectively in HF and TMAH solution, respectively (Fig. 2(f)). To precise control the top Ge channel thickness, a series of low damage etching process was adapted to thin down Ge (Fig. 2(g)). The realized double channel structure is fully isolated with an insulating insertion layer,[5] which is very promising for realizing novel complementary FET (CFET) with minimum process steps. The cross-sectional TEM image of Ge/Si stacked channel of CFET after high k metal gate process is demonstrated in Fig. 2(h). Even more multiple stacks can be realized by using LT-HBT. A vertically stacked three-layer structure with 2 bottom Si layers and 1 top Ge layers is also demonstrated using SOI-based donor wafers in Fig. 3, indicating the highly integrated density channel structure is possible. The feasibility of layer transfer technology has been proved for multi-channel structure with high mobility channels for N2 node and beyond. Acknowledgement This work was supported by JST Japan-Taiwan Collaborative Research Program, Grant Number JPMJKB1902, Japan and the Ministry of Science and Technology under Grant Number MOST-109-2628-E-492-001-MY3, 109-2923-E-492-001-MY3, 107-2221-E-492-016-MY3.

β-Ga2O3 vertical heterojunction barrier Schottky diodes terminated with p-NiO field limiting rings

In this Letter, high-performance β-Ga2O3 vertical heterojunction barrier Schottky (HJBS) diodes have been demonstrated together with the investigation of reverse leakage mechanisms. In HJBS configurations, NiO/β-Ga2O3 p-n heterojunctions and p-NiO field limiting rings (FLRs) are implemented by using a reactive sputtering technique at room temperature without intentional etching damages. Determined from the temperature-dependent current-voltage characteristics, the reverse leakage mechanism of the HJBS diode is identified to be Poole-Frenkel emission through localized trap sates with an energy level of EC-0.72 eV. With an uniform FLR width/spacing of 2 μm in HJBS, a maximum breakdown voltage (BV) of 1.89 kV and a specific on-resistance (Ron,sp) of 7.7 mΩ·cm2 are achieved, yielding a high Baliga's figure-of-merit (FOM, BV2/Ron,sp) of 0.46 GW/cm2. The electric field simulation and statistical experimental facts indicate that the electric field crowding effect at device edges is greatly suppressed by the shrinkage of p-NiO FLR spacing, and the capability of sustaining high BV is enhanced by the NiO/β-Ga2O3 bipolar structure, both of which contribute to the improved device performance. This work makes a significant step to achieve high performance β-Ga2O3 power devices by implementing alternative bipolar structures to overcome the difficulty in p-type β-Ga2O3.

Dry Etching Damage and Alloy Composition Analysis of GaN-Based Semiconductors Using Electron Energy-Loss Spectroscopy

Dry Etching Damage and Alloy Composition Analysis of GaN-Based Semiconductors Using Electron Energy-Loss Spectroscopy

Investigations of Sidewall Passivation Technology on the Optical Performance for Smaller Size GaN-Based Micro-LEDs

Micro-light emitting diodes (Micro-LEDs) based on III-nitride semiconductors have become a research hotspot in the field of high-resolution display due to its unique advantages. However, the edge effect caused by inductively coupled plasma (ICP) dry etching in Micro-LEDs become significant with respect to the decreased chip size, resulting in a great reduction in device performance. In this article, sector-shaped GaN-based blue Micro-LEDs are designed and fabricated. Additionally, the device performance of different size Micro-LEDs with passivation are investigated with respect to those without passivation. Several methods have been applied to minimize the etching damage near the edge, including acid-base wet etching and SiO2 passivation layer growth. The room temperature photoluminescence (PL) results demonstrate that the light emission intensity of Micro-LEDs can be significantly enhanced by optimized passivation process. PL mapping images show that the overall luminescence of properly passivated Micro-LEDs is enhanced, the uniformity is improved, and the effective luminescence area is increased. The recombination lifetime of carriers in Micro-LEDs are increased by the usage of passivation process, which proves the reduction in non-radiative recombination centers in Micro-LEDs and improved luminescence efficiency. As a result, the internal quantum efficiency (IQE) is improved from 14.9% to 37.6% for 10 μm Micro-LEDs, and from 18.3% to 26.9% for 5 μm Micro-LEDs.

Vertical MBE growth of Si fins on sub-10 nm patterned substrate for high-performance FinFET technology* *Project supported by the National Key Research and Development Program of China (Grant No. 2016YFA0200504) and the National Natural Science Foundation of China (Grant No. 61927901).

A high quality epitaxial Si layer by molecular beam epitaxy (MBE) on Si (001) substrates was demonstrated to fabricate a channel with low density defects for high-performance FinFET technology. In order to study the effects of fin width and crystallography orientation on the MBE behavior, a 30 nm thick Si layer was deposited on the top of an etched Si fin with different widths from 10 nm to 50 nm and orientations of 〈100〉 and 〈110〉. The result shows that a defect-free Si film was obtained on the fin by MBE, since the etching damage was confined in the bottom of the epitaxial layer. In addition, the vertical growth of the epitaxial Si layer was observed on sub-10 nm 〈100〉 Si fins, and this was explained by a kinetic mechanism.

High Breakdown Electric Field MIS-Free Fully Recessed-Gate Normally Off AlGaN/GaN HEMT With N2O Plasma Treatment

In this article, the AlGaN barrier fully removed recessed-gate normally off AlGaN/GaN high electron mobility transistors (HEMTs) with N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O plasma treatment are fabricated. The low speed and low damage etching is used in recessed-gate etching, the etching depth is about 26 nm with 0.4 nm remaining, and then, the remaining barrier layer is oxidized by N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O plasma treatment. In the terms of devices' characteristics, the threshold voltage of the recessed-gate HEMT is +1.5 V, and the channel current of recessed-gate HEMTs at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> - V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TH</sub> = 1.5 V is about 110 mA/mm. Moreover, 14 mV/V of drain-induced barrier lowering (DIBL) and 70 mV/decade of subthreshold slope (SS) are achieved. More importantly, the fully recessed-gate HEMT shows the average breakdown electric field at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">G</sub> = 0 V of about 0.64 MV/cm, which is a very high value in the fully normally off recessed-gate HEMTs without metal insulator semiconductor (MIS) structure, which will be beneficial to the application of this device in the low power supply topology circuit.

Fabrication and repair of GaN nanorods by plasma etching with self-assembled nickel nanomasks

High crystal quality GaN nanorod arrays were fabricated by inductively coupled plasma (ICP) etching using self-organized nickel (Ni) nano-islands mask on GaN film and subsequent repaired process including annealing in ammonia and KOH etching. The Ni nano-islands have been formed by rapid thermal annealing, whose density, shape, and dimensions were regulated by annealing temperature and Ni layer thickness. The structural and optical properties of the nanorods obtained from GaN epitaxial layers were comparatively studied by high-resolution X-ray diffraction (HRXRD), Raman spectroscopy and photoluminescence (PL). The results indicate that damage induced by plasma can be successfully healed by annealing in NH3 at 900 °C. The average diameter of the as-etched nanorod was effectively reduced and the plasma etch damage was removed after a wet treatment process in a KOH solution. It was found that the diameter of the GaN nanorod was continuously reduced and the PL intensity first increased, then reduced and finally increased as the KOH etching time sequentially increased.

Low-Damage and Self-Limiting (Al)GaN Etching Process through Atomic Layer Etching Using O2 and BCl3 Plasma

This paper reports on the use of low-damage atomic layer etching (ALE) performed using O2 and BCl3 plasma for etching (Al)GaN. The proposed ALE process led to excellent self-limiting etch characteristics with a low direct current (DC) self-bias, which resulted in a high linearity between the etching depth and number of cycles. The etching damage was evaluated using several methods, including atomic force microscopy, photoluminescence (PL), and X-ray photoelectron spectroscopy, and the I–V properties of the recessed Schottky diodes were compared with those of digital etching performed using O2 plasma and HCl solution. The electrical characteristics of the recessed Schottky diode fabricated using the proposed ALE process were superior to those of the diodes fabricated using the conventional digital etching process. Moreover, the ALE process yielded a higher PL intensity and N/(Al + Ga) ratio of the etched AlGaN surface, along with a smoother etched surface.

Enhancement in external quantum efficiency of AlGaInP red \u03bc-LED using chemical solution treatment process

To investigate the effects of their surface recovery and optical properties, extremely small sized (12 µm × 12 µm mesa area) red AlGaInP micro light emitting diodes (upmu LED) were fabricated using a diluted hydrofluoric acid (HF) surface etch treatment. After the chemical treatment, the external quantum efficiencies (EQEs) of upmu-LED at low and high injection current regions have been improved by 35.48% and 12.86%, respectively. The different phenomena of EQEs have a complex relationship between the suppression of non-radiative recombination originating from the etching damage of the surface and the improvement of light extraction of the sidewalls. The constant enhancement of EQE at a high injection current it is attributed to the expansion of the active region’s sidewall surface area by the selective etching of AlInP layers. The improved EQE at a low injection current is related to the minimization of the surface recombination caused by plasma damage from the surface. High-resolution transmission electron microscopy (HR-TEM) revealed physical defects on the sidewall surface, such as plasma-induced lattice disorder and impurity contamination damage, were eliminated using chemical treatment. This study suggests that chemical surface treatment using diluted HF acid can be an effective method for enhancing the upmu-LED performance.