Etch CD Research Articles

Enhanced Equipment and New Processes As Enabler for Power Technologies on 300mm Substrates

Transferring power technologies from 200mm silicon substrates to 300mm provides challenges with regard to very special substrate materials, process equipment, and unit processes in addition to those faced by a similar transfer of CD driven commodity products as DRAMS and MPUs. Due to the fact that the current path leads vertically through the substrate and that the final substrate thickness thus determines the figure of merit, the electrical resistance of the device in on-state, ultra-thin wafer handling for wafer backside processing is a further specialty and hence challenge for power semiconductors manufacturing. Current furnace equipment for standard CMOS is capable of processing at temperatures up to 1000°C whereas power technologies require furnace temperatures up to 1200°C which requires hardware adaptation of the tools to comply reliably with these requirements. Some applications furthermore require temperature uniformity within very narrow intervals across the wafers within wafer batches. Wafers with polysilicon films on the wafer backside for impurity gettering are so far only available on 200mm. Such gettering films were deposited and analytically assessed with regard to their gettering capabilities. The extremely high doped wafer substrates for manufacturing power devices are not available yet from the suppliers in both sufficient quality and quantity to start 300mm power semiconductor activities. These substrates have to be manufactured by the semiconductor manufacturer by epitaxial growth. In addition to severe modifications of the epitaxial reactors and the provision of the complete infrastructure that allows running such processes under safe operation conditions unit process development is very challenging. Simultaneous achievements of both supreme uniformity of thick epitaxial layers and of the dopant distribution therein is key to allow perfect pattern generation and transfer and identical electrical device performance respectively all across the wafer until the very wafer edge to take full advantage of the productivity advantage of large diameter wafer processing. All the activities to improve tools and hence processes, were severely supported by equipment and process simulation. To boost productivity additionally to processing 300mm diameter wafers the use of a batch epitaxial tool has been envisioned for the growth of very thick and high resistivity silicon for IGBT applications. All the tool and process learning done on a 5-wafer 200mm batch tool will be used for the design and manufacturing of a similar tool type processing 300mm substrate. For this application high focus was posed on the reduction of sliplines, irregularities in film growth with atomic scale heights, resulting from non-uniform temperature coupling to the substrates in process. While critical CDs in high end products differ by almost an order of magnitude between power semiconductors and standard CD driven CMOS technologies, the tolerated CD uniformities are rather comparable. This finally requires for pattern transfer advanced plasma etch equipment with all the “knobs” to address wafer center and wafer periphery individually regarding etch rate, profile shape, and CD to achieve lowest center-edge non-uniformities. The various tool and process aspects of 300mm power semiconductor manufacturing will be addressed and reviewed in this talk. The work has been performed in the project EPT300, co-funded by grants from Austria, Germany, Italy, The Netherlands and the ENIAC Joint Undertaking.

Enhanced Equipment and New Processes As Enabler for Power Technologies on 300mm Substrates

The customized substrates for manufacturing 300mm power semiconductors had to be prepared by deposition processes and epitaxial growth on standard substrates since they were not yet available from suppliers in both sufficient quality and quantity. Polysilicon films were deposited on wafer backsides and optimized regarding impurity gettering. Severe modifications of existing epitaxy reactors, the facilitation, and the infrastructure were prerequisite to develop extremely high doped, thick silicon layers with both supreme uniformity of layer thickness and dopant distribution to take full advantage of the productivity advantage of large diameter wafer processing. Simulation supporting these activities was also key to enable furnace processes with extremely tight temperature ranges. For the development of very thick, high resistivity silicon layers a 5-wafer 200mm batch tool was used to exploit the tool and process learning for the design and manufacturing of a similar 300mm batch tool. For pattern transfer the same advanced plasma etch equipment was mandatory to achieve similarly uniformities regarding etch rate, profile shape, and CD as in CD-driven advanced DRAMs and MPUs.

Strategy of DoseMapper (DoMa) Application and Monitor for Critical Dimension Uniformity (CDU) Control in Sub-45nm Gate Process

As the industry enters 45/40 nm technology node and beyond, the effective control of polysilicon gate's critical dimension uniformity (CDU) becomes more important to device performance. However, to achieve good uniformity is very challenging since the CDU has shown high sensitivities to the variations from resist track recipe, scanner variation, and etcher. It is well known, the DoseMapper (DoMa) is a highly effective tool for the improvement of CDU. In this paper, we will focus on the set up of a DoMa application and monitor system for 40 nm poly gate CDU improvement. Through the use of a state of the art immersion exposure tool (ASML 1900Gi), a DoMa application can successfully improve a gate across wafer CDU by 49% in 40 nm node. In addition, DoMa is more effective when it is applied at post-etch stage than at post-litho stage because it can cover the systematic etch CD variation. However, when a DoMa recipe is applied at post-etch stage, at post-litho, the CDU is no longer meaningful. Before the wafer is etched, we need a new metric to monitor the DoMa performance. A new DoMa monitoring system by RSQ function at post-litho has been introduced and the result will be presented in this paper, which can monitor CD map change by SPC (Statistics Process Control) alarm function.

Reverse Phase Solution for Mesa Chamber Uniformity Improvement

Applied Materials® newly launched advanced 300mm plasma etcher, Mesa® chamber implemented many key hardware modification to provide much more robust process knobs to improve the depth uniformity and CD uniformity for critical applications of <32nm technology. The new features including DMC,MRAD and others features focus on the innovation of Top ICP Source to optimize ion flux distribution uniformity to improve the Etch Rate uniformity and CD uniformity. As result the whole wafer uniformity can achieve 1~1.5nm (3σ). This article will focus on two of new features: DMC and MRAD which can solve the special distribution map to further improve uniformity significantly. The discussion includes hardware fundamental introduction and plasma simulation result as well as supporting wafer result.

17.1: Novel Patterning Process for Mask Reduction

AbstractIn this paper, a 3mask IPS mode TFTLCD panel is introduced by using a new ITO patterning process. The key processes are the CHF process and new ITO etch process which is related to selective crystallization on SiNx layer. In addition, the change of etch CD bias direction from 1dimension to 2dimension reduces or eliminates the MURA defects in panel due to the variation of the distance between pixel and common electrodes.

Detailed Placement for Enhanced Control of Resist and Etch CDs

Subresolution assist feature (SRAF) and etch-dummy-insertion techniques have been absolutely essential for process-window enhancement and CD control in photo and etch processes. However, as focus levels change during lithography manufacturing, CDs at a given ldquolegalrdquo pitch can fail to achieve manufacturing tolerances. Placed standard-cell layouts may not have the ideal whitespace distribution to allow for an optimal assist-feature insertion. This paper first describes a novel dynamic-programming-based technique for Assist-Feature Correctness (AFCorr) in detailed placement of standard-cell designs. At the same time, etch-dummy features are used in the mask data preparation flow to reduce CD skew between resist and etch processes and to improve the printability of layouts. However, etch-dummy rules conflict with the SRAF insertion because each of the two techniques requires specific design rules. We further present a novel SRAF-aware etch-dummy-insertion method (SAEDM) which optimizes the etch-dummy insertion to make the layout more conducive to the assist-feature insertion after the etch-dummy features have been inserted. Since placement of cells can create forbidden-pitch violations of resist process and can increase etch skew, the placer must also generate etch-dummy-correct placement. This can be solved by Etch-dummy Correctness (EtchCorr), which is an intelligent whitespace management for etch-dummy-corrected placement, an extension of the AFCorr methodology. These methods for enhanced resist and etch CD controls are validated on industrial test cases with respect to wafer printability, database complexity, and device performance. For benchmark designs, we validate the four methodologies: 1) AFCorr; 2) SAEDM; 3) AFCorr SAEDM; and 4) AFCorr EtchCorr SAEDM. The AFCorr placement perturbation achieves a significant reduction in forbidden pitches between polysilicon shapes. Using 1) flow, forbidden-pitch count of photo process is reduced by 76%-100% for 130 nm and by 87%-100% for 90 nm. Our novel Corr design-perturbation technique, which combines the AFCorr and EtchCorr methods, facilitates additional SRAF and etch-dummy insertions and, thus, reduces the CD skew between the photo and etch processes. After Corr with SAEDM, edge-placement-error count is also reduced by 91%-100% in the resist CD and by 72%-98% in the etch CD. Our methods provide a substantial improvement in CD control with negligible timing, area, and CPU overhead. The advantages of such correctness methods are expected to increase in future technology nodes.