ESD Test Research Articles

Transmission line pulse ESD testing of giant magnetoresistive recording heads

The behavior of giant magnetoresistive recording heads during transmission line pulse (TLP) testing is reported for the first time. The design of a simple TLP tester is described and used to produce current pulses with widths from 0.8 to 40 ns. The TLP tester was used with a quasistatic R(H) tester to measure the resistance and magnetic damage to the recording head. It is concluded that an easily built TLP tester is useful for producing high current pulses of varying width for electrostatic discharge testing of recording heads.

Impact of ESD protection device trigger transient on the reliability of ultra-thin gate oxide

Common ESD protection devices have a snapback characteristic similar to a silicon-control rectifier. The transient voltage required to trigger these devices usually is not an important design criterion as long as it is not too high. In this work, it is demonstrated that the defect generation mechanism in oxide during electrical stress remains unchanged in the sub-nanosecond stress regime. As a result, the voltage transient can create far more defects in the gate oxide than the main ESD event clamped at the holding voltage. Due to difficulty in measurement, this oxide reliability degradation can lead to chip failure but not show up in simulated ESD test.

A strategy for characterization and evaluation of ESD robustness of CMOS semiconductor technologies

This paper proposes an ESD technology strategy for characterization, evaluation and benchmarking the ESD “robustness” of CMOS semiconductor technologies. The ESD methodology uses a set of CMOS “building block” ESD test structures, matrices of critical ESD layout variables, electrical characterization parameters, and testing and extraction procedures, and ESD metrics. This work is the first step in the development of a common ESD language.

A study of diode protection for giant magnetoresistive recording heads

ESD testing of giant magnetoresistive (GMR) heads with diode protection is described. While the use of diodes did increase the magnetic and failure voltages of the GMR head, the magnetic failure voltage was increased much less than the resistance failure voltage. This results in an unfortunate side effect, which is to dramatically increase the range over which magnetic damage occurs without a corresponding resistance change. This problem was especially clear for the case of two diodes in series. The current flow through the GMR head and diode were measured and agreed with SPICE circuit simulation results. The difference between magnetic and resistance protection is due to the nonlinear clamping behavior of the diode. We conclude that serious magnetic damage will be the predominant failure signature for GMR heads with ESD protect diodes.

Sensitivity of multimode bidirectional optoelectronic modules to electrostatic discharges

Human Body Model ESD tests on two commercially available different types of wavelength division multiplexing bidirectional optoelectronic modules, intended for data transmission over multimode optical fibers at 820 and 1320 nm wavelengths, have been performed. These bidirectional modules incorporated pin diode receivers and light emitting diode in a single package. In particular, the 820 nm light emitting diodes had rather high damage threshold pulse amplitudes of about +10,000 V under forward bias and −5000 V under reverse bias conditions, and no active layer degradation has been observed. In-situ measurements of the optical transients emitted during forward bias ESD pulses enabled a damage pulse threshold detection of a LED without the need of further optoelectronic characterization. The receiver photodiodes, however, were very sensitive to reverse bias ESD pulses. The InGaAs photodiodes degraded during ESD pulses with amplitudes as low as −150 V and in the case of the Silicon photodiodes as low as −175 V.

Unique ESD failure mechanisms during negative to Vcc HBM tests

HBM ESD tests on two types of 0.6 μm DRAM devices showed that internal circuit or output driver failures would occur after the input or I/O pins were ESD stressed negative with respect to Vcc at ground. These failures occurred at lower than expected ESD stress voltages due to power-up circuit interactions that either turned-on unique internal parasitic ESD current paths or disrupted the normal operation of the output pin’s ESD protection circuit. ESD analysis found there exists a set of power-up sensitive circuits and if placed near a Vcc bond pad can result in low voltage ESD failures.

Component level ESD testing

This paper reviews different aspects of ESD component level testing. Traditional and alternate test methods are addressed. Focus topics are the device-under-test to tester interaction, the tester specifications and parasitics, the test procedures and test result reproduction and correlation. The purpose of the paper is to serve as a tutorial on the subject of Component Level ESD Testing.

Dangerous parasitics of socketed CDM ESD testers

HBM, non-socketed and socketed CDM testing were performed on HF-ICs. By applying HBM and non-socketed CDM stress weak pins were located by selective stress. Socketed CDM, however, caused a damage at the weak pins, even when they were excluded from testing. Socketed and non-socketed CDM caused the same electrical failure signature. After insulating the weak pins from the tester circuitry, these pins survived the socketed CDM test without damage and the failure threshold increased. This behaviour is explained by the discharge of the parasitic tester capacitance through the weak pins, while other pins are tested.

ESD tester parasitics and stress conditions and their impact on device failure levels and failure mechanisms

A comparative study of Human Body and Machine Model (HBM/MM) testers is performed using a very large sample size for statistical significance. Failure mechanisms and types of damage are categorized with the use of photoemission spectrum analysis. Tester parasitic values are extracted for each machine, and a correlation is established to failure thresholds, distributions and failure mechanisms.

Risetime effects of HBM and square pulses on the failure thresholds of GGNMOS-transistors

For 0.8μm-GGNMOS transistors a lack of correlation between Human Body Model ESD testers conforming to current standards and transmission line pulsing (TLP) was observed. The paper demonstrates the influence of the initial 5%–40% risetime of TLP testers on the failure thresholds and failure signatures of transistors with single and multiple fingers.

ESD: waveform calculation, field and current of human and simulator ESD

Currents, current derivatives and transient fields of human ESDs are compared to currents and fields caused by commercial simulators. The results point at undefined but influential parameters of simulators and the standardized setup used. Suggestions for possible improvements of ESD test standards are given. A calculation method for the ESD current is provided. This method includes an arc model. Possible high peak current values ( > 10 A/kV) are validated by a simple physical model of the hand-metal piece geometry. By calculation it is shown under which circumstances human ESD currents come close to the standardized waveform of simulators.

Melt filaments in n +pn + lateral bipolar ESD protection devices

Lateral bipolar n +pn + devices, with thick field oxide (TFO) separating the collector and emitter, are often used in snapback mode as protection devices for MOS ESD circuit protection. ESD testing for human body model (HBM), machine model (MM) and charged device model (CDM) waveforms was performed on a family of TFO cells which varied the gate length (bipolar base width) as the experimental parameter. For MM and CDM, the data showed a dependence of withstand voltage on the gate length, indicating that longer gate lengths improve performance; while for HBM, withstand voltage was independent of the gate length. The devices exhibited failure modes that manifested as low-level current leakage. Failure analysis identified the current leakage sites as melt filaments primarily localized at the TFO ends. Filament distribution was seen to be a function of gate length for MM. Two possible mechanisms are presented to account for the observed filament distribution and follow-up experiments are suggested to test the validity of each.

Analysis of snubber-clamped diode-string mixed voltage interface ESD protection network for advanced microprocessors

A novel snubber-clamped diode-string ESD protection circuit for mixed voltage interface microprocessor applications is described. Analytical models, circuit simulation, electrical characterization, ESD electrothermal simulation, and ESD test data, will be shown for shallow trench isolation (STI) and LOCOS CMOS technologies.

Compact electro‐thermal simulation of ESD‐protection elements

AbstractNumerical simulations at the circuit level can improve the understanding of the behaviour of protection structures under system aspects. Full protection circuits with the influence of HBM ESD tester parasitics and additional parasitic elements in the circuitry have been investigated. Compact electro‐thermal models for single protection elements (diodes and snapback nMOSFETs) have been developed. They help to explain differences between expected ESD‐hardness and HBM‐failure thresholds of protection structures.

Analysis of soft breakdown failure with ESD on output buffer nMOSFETs and its improvement

The leakage increase of the off-state MOSFETs after an ESD event has been studied for output transistors with the thin gate oxide and LDD structures. Leakage increase called has been found at relatively low ESD testing voltages (200-300 V). This soft breakdown is caused by the creation of interface traps due to the snap-back stressing during the ESD event. The creation of interface traps has enhanced the interface trap to band tunneling current at the drain side of the MOSFETs. The improvement of the ESD threshold has also been proposed with an additional arsenic implantation into the n/sup $/region. It has been confirmed that the arsenic implantation improved the HBM ESD threshold to more than 2000 V. >

Degradation in InGaAsP semiconductor lasers resulting from human body model ESD

Human Body Model (HBM) ESD testing has been performed on commercial, multi-frequency InGaAsP semiconductor lasers for the purpose of identifying the relationship between ESD-induced degradation and parametric changes. Step stressing performed on lasers manufactured from 5 different wafers reveals a strong wafer dependence of forward biased failure voltage. In addition, a correlation is reported between unstressed spectral perturbations and the ESD failure voltage. A first order, rate equation model is used to simulate the variation in threshold current with ESD stress voltage. Results indicate that threshold current increases slowly with stress at voltages below the failure voltage and rapidly increases above the failure voltage, in agreement with experimental observations.

New experimental results in the qualification tests of large EPROMs

Qualification of large EPROMS has to cover tests for all essential characteristics of nonvolatile memories. Data retention is one of the most important aspects. The characterization is performed in a Sentry S50 VLSI automatic test equipment at five temperatures with supply voltages between 3V and 6.5 V. For this characterization worstcase combinations of supply voltage and temperature are given. Three data retention bakes at 125°, 200° and 300°C with and without preceding stresses (ESD, programming) point out the influence of temperatures and stresses on the margin voltage, which can be taken as an indicator of the data retention capability. Important results are obtained from the characterization, the ESD tests, the data retention bakes, and the burn-in. 6 manufacturers, each with 245 c are investigated. Differences between the manufacturers are obvious. A reduced procedure for testing and qualifying large EPROMS as well as an outlook on the future research activities are given.

System ESD immunity design

System modeling of the charge source and paths of the primary and possible secondary discharges in an ESD event are shown to be complicated. Five design approaches are given to avoid ESD effects. After a review of air discharge characteristics, the control of ESD arc current is illustrated for the standard equipment ESD test method. It is pointed out that all AC main ESD testers need a special very high frequency filter to create realistic testing.