Abstract
The leakage increase of the off-state MOSFETs after an ESD event has been studied for output transistors with the thin gate oxide and LDD structures. Leakage increase called has been found at relatively low ESD testing voltages (200-300 V). This soft breakdown is caused by the creation of interface traps due to the snap-back stressing during the ESD event. The creation of interface traps has enhanced the interface trap to band tunneling current at the drain side of the MOSFETs. The improvement of the ESD threshold has also been proposed with an additional arsenic implantation into the n/sup $/region. It has been confirmed that the arsenic implantation improved the HBM ESD threshold to more than 2000 V. >
Published Version
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