ESD Protection Elements Research Articles

Simulation of ESD Thermal Failures and Protection Strategies on System Level

In this paper, approaches for the modeling and simulation of thermal destruction of ICs due to ESD are discussed from a system point of view. Considered systems consist of ESD generator, PCB, protection element, and IC. A direct connection between the ESD generator and the system is always assumed. For the modeling of an IC ESD destruction, the electric behavior model of an IC pin to ground or supply is extended with a thermal destruction model. The thermal model consists mainly of a thermal resistance and a thermal capacitance. When structure temperature reaches a threshold, a failure is assumed. All needed model parameters can be found with a set of measurements and tests. No internal knowledge of the IC or protection element structures is required. The methodology was applied to several ICs, protection elements, and system structures with emphasis on automotive electronics. All needed component model parameters were generated from measurements. Models and parameter measurements are described. Results from the system simulation were compared to system test results with hardware. In most cases, the simulation could predict well the destruction behavior of a system. Thermal failure and safe operating area prediction quality are compared. The described simulation method helps with selection of protection strategies and optimization of system ESD robustness.

Source-End Layout Influences on MOSFET ESD Protection Devices in a 0.35um 5V Process

An nMOS transistor in input/output pad as the ESD protection element is usually in the form of multi-finger layout. This paper will show simple but effective ways to improve an nMOSFET’s ESD robustness or LU immunity for use in I/O pads, i.e., the source-end layout influences on the protection components in ESD/LU capabilities of the input/output pads will be investigated. In other words, they are used to increase the effective ESD or LU capability of the ESD protection elements. Here, the different source-end layout types will be carried out the important snapback parameters. We focus on exploring the secondary breakdown current (It2) and holding voltage (Vh) for the ESD discharge capability and the latch-up immunity, hopefully, it does effectively enhance ESD/LU robustness.

Determination of self-heating and thermal resistance in polycrystalline and bulk silicon resistors by DC measurements

Self-heating of silicon resistors (fabricated in polycrystalline and bulk silicon) which are used as passive devices in analog circuits and as ESD-Protection elements is characterised in this work by purely DC measurements. A methodology using the device simultaneously as heater and temperature sensor is presented. Extraction of thermal resistance is derived and discussed. Different types of resistors including a wide range of different geometries are characterised, the geometry dependence of the thermal resistance is determined for different resistor types. Theoretical models describing geometry dependence for thermal resistance are in very good agreement with the presented results.

Design and Optimization of Vertical SiGe Thyristors for On-Chip ESD Protection

We present extensive measurement results investigating the design and optimization of vertical SiGe thyristors for use as ESD protection elements in RF integrated circuits. Experiments include variations of the anode material, contact geometry, and buried layer, as well as a detailed study of optimal area scaling. RF characterization using S-parameter data is presented.

Investigation of ESD protection elements under high current stress in CDM-like time domain using backside laser interferometry

Switching dynamics and current flow homogeneity under very-fast TLP (vf-TLP) stress is investigated in smart power and CMOS technology ESD protection devices by means of optical transient interferometric mapping (TIM) techniques with sub-nanosecond time resolution. Comparison between the device behavior under vf- and conventional TLP stress is discussed. The sub-ns time resolution enables a detailed insight into the triggering behavior of protection elements.

Experimental and simulation analysis of a BCD ESD protection element under the DC and TLP stress conditions

Experimental and simulation analysis of a BCD ESD protection element under the DC and TLP stress conditions

Analyzing the switching behavior of ESD-protection transistors by very fast transmission line pulsing

This work describes, how the very fast transmission line pulsing (VFTLP)-technique can be used to characterize the switching behavior of ESD protection elements. In a first application we investigate the behavior of a protection element consisting of a lateral and vertical transistor part. This element shows a good ESD performance under 100 ns-TLP and HBM conditions. Under CDM relevant conditions, however, we could identify by means of VFTLP a delayed triggering of the vertical transistor part, which leads to an increased maximum voltage and thus to a low-failure threshold. In the second application we propose a methodology for the extraction of the base transit time parameter which improves the accuracy of a compact transistor model during turn on.

Layout optimization of an ESD-protection n-MOSFET by simulation and measurement

This paper presents a new method for optimizing the performance of a lateral npn-transistor used as ESD protection element. Relying on process modeling and electrothermal device simulation we are able to use device-internal quantities such as the electric field or the temperature distribution to find the optimal transistor layout. Guided by simulation, we are able to guarantee a uniform avalanche breakdown of a single meander-like collector junction. Experimental results from measurements show that this is crucial for better ESD performance of a spatially efficient device. Our optimized device reaches 83% of the second breakdown trigger current of a straight device. Compared to an unoptimized meander-like device, we could increase its performance by 53%. The good agreement between measurements and simulation for different transistor shapes validates our methodology and approach to optimization of ESD devices.

ESD protection elements during hbm stress tests—further numerical and experimental results

AbstractCorrelation problems for HBM‐ESD testing result from the complex interaction between device and tester. The HBM stresses of different well‐characterized testers1.2 are applied to protection elements. By means of circuit simulations and in situ measurements, snapback and second breakdown during HBM are investigated. For fast transient events, a new transmission line approach of the tester improves the correlation between experiment and simulation.

Editorial

Quality and Reliability Engineering InternationalVolume 10, Issue 4 p. 253-253 EditorialFree Access Editorial N. Labat, N. Labat IXL—(URA 846-CNRS) University of Bordeaux 351 Cours de la Libération 33405 Talence, FranceSearch for more papers by this authorA. Touboul, A. Touboul IXL—(URA 846-CNRS) University of Bordeaux 351 Cours de la Libération 33405 Talence, FranceSearch for more papers by this author N. Labat, N. Labat IXL—(URA 846-CNRS) University of Bordeaux 351 Cours de la Libération 33405 Talence, FranceSearch for more papers by this authorA. Touboul, A. Touboul IXL—(URA 846-CNRS) University of Bordeaux 351 Cours de la Libération 33405 Talence, FranceSearch for more papers by this author First published: 1994 https://doi.org/10.1002/qre.4680100402AboutPDF ToolsRequest permissionExport citationAdd to favoritesTrack citation ShareShare Give accessShare full text accessShare full-text accessPlease review our Terms and Conditions of Use and check box below to share full-text version of article.I have read and accept the Wiley Online Library Terms and Conditions of UseShareable LinkUse the link below to share a full-text version of this article with your friends and colleagues. Learn more.Copy URL No abstract is available for this article. References 1 A. Birolini, Quality and Reliability of Technical Systems, Springer Verlag, Berlin, 1994. 2 W. Gerling, Integration of efforts for the reliability of microelectronic devices, Quality and Reliability Engineering International, 10, 255– 261 (1994) — this issue. 3 J. F. Verweij, A. C. Brombacher and M. M. Lunenborg, ‘Component lifetime modelling,’ Quality and Reliability Engineering International, 10, 263– 271 (1994) — this issue. 4 C. Russ, H. Gieser, P. Egger and S. Irl, ‘Compact electrothermal simulation of ESD-protection elements’, Quality and Reliability Engineering International, 10, 335– 340 (1994) — this issue. 5 J. R. Lloyd, ‘Reliability modelling for electromigration failure’, Quality and Reliability Engineering International, 10, 303– 308 (1994) — this issue. 6 W. Claeys, V. Quintard, S. Dilhaire, D. Lewis and Y. Danto, ‘Early detection of ageing in solder joints through laser probe thermal analysis of the Peltier effect’, Quality and Reliability Engineering International, 10, 289– 295 (1994) — this issue. Volume10, Issue41994Pages 253-253 ReferencesRelatedInformation