ESD Protection Devices Research Articles

The synergistic design of 5 V ESD protection applications using two holding voltage improving methods

In this paper, a series of Low Voltage Triggering Silicon-Controlled Rectifier (LVTSCR)-based devices were designed and fabricated in a 0.25 μm Bipolar-CMOS-DMOS (BCD) process. Two distinct methods, the integration of additional doping regions and current paths, are investigated to improve the proposed devices’ holding voltage (Vh). Two-dimensional device simulation is employed to elucidate the working mechanism of these ESD protection devices, complemented by the introduction of a transmission line pulse (TLP) measuring system to assess their ESD protection capabilities. Comparative analysis of TLP results reveals that both methods contribute significantly to the augmentation of holding voltage in LVTSCR ESD protection devices. The refined structure, LVTSCR_BN, with two additional current paths, surface and buried, demonstrated a noticeable increment in holding voltage. With its holding voltage of 7.619 V and trigger voltage of 10.61 V, LVTSCR_BN is proved suitable for the ESD protection of circuits operating at the voltage of 5 V.

Asymmetric Early Leakage Failure in Bi-Directional SCR ESD Protection Device in BCD Technology

Asymmetric Early Leakage Failure in Bi-Directional SCR ESD Protection Device in BCD Technology

High-Voltage ESD Protection Devices With High Robustness of 13 kV and Strong Radiation Tolerance up to 200 krad(Si)

High-Voltage ESD Protection Devices With High Robustness of 13 kV and Strong Radiation Tolerance up to 200 krad(Si)

Robustness-Improved ESD Protection Devices With Low Leakage Using Middle Silicon Layer in Double SOI Technology

Robustness-Improved ESD Protection Devices With Low Leakage Using Middle Silicon Layer in Double SOI Technology

Optimized PNP ESD Protection Device With Adjustable Trigger and Holding Voltages for High-Voltage Applications

Optimized PNP ESD Protection Device With Adjustable Trigger and Holding Voltages for High-Voltage Applications

A novel dual-directional DTSCR in twin-well process for ultra-low-voltage ESD protection

By embedding additional NPN- and PNP- type bipolar junction transistors into a diode-triggered silicon-controlled rectifier (DTSCR) with single-directional ESD protection, we propose and implement a novel dual-directional DTSCR (DDTSCR) by using the twin-well process in a 0.18-µm CMOS process that provides highly efficient ultra-low-voltage ESD protection. Compared to conventional DTSCRs, the failure current of the proposed DDTSCR increases from 4.5 A to 5.6 A, successfully passing the ESD level tests of human body model at 8 kV and machine model at 650 V. Owing to its unique structural design and metal routing, the ESD protection efficiency of the DDTSCR is twice that of the DTSCR. By adopting a new E-shaped layout (DDTSCR-E), the failure current under positive stress can increase further to 6.6 A. In order to verify the ESD protection performance stabilization with different processes, the DDTSCR-E is fabricated in the 0.18-µm BCD, 0.18-µm and 21-nm CMOS processes, respectively. The trigger voltage of DDTSCR-E is found more stable than other ESD characteristics during the process migration. The high efficiency, the strong ESD robustness and the stable process migration make the proposed DDTSCR a promising ESD protection device for ultra-low-voltage integrated circuits.

A Physics-Based Model for Snapback-Type ESD Protection Devices

A Physics-Based Model for Snapback-Type ESD Protection Devices

Design, Fabrication and Measurement of LDNMOSSCR Devices with Appropriate ESD Protection Window for 18V HV CDMOS Process

LDMOS embedded SCR is a normal way to improve the ESD robustness for smart power technologies, but it doesn’t always have the proper ESD window for a given application. In this paper, LDNMOS-SCR of four variants structures have been inves-tigated based on a high-voltage (HV) 0.5μm 18V HV CDMOS process with 2D device simulation and silicon verification. TLP testing results demonstrated that those devices successfully elevate the second breakdown current I t2 from original 1.146A to above 3A; source isolated device has a lower V t1 (45.79V) than source non-isolated devices; the V h of the four devices is related to their structure, and their I h are all above 800mA, which is big enough to ensure the latch-up immunity under ESD stresses in HV applications. The device with its source isolated from PSUB is the suitable ESD protection device for HV 18V CDMOS technology owning to its strong ESD robustness, low V t1 , small R on and sufficiently big I h .

Design of high-reliability LDO regulator with SCR based ESD protection circuit using body technique and load transient detection

External capacitors in conventional LDO regulators can reduce transient response characteristics such as overshoot and undershoot. However, the capacitor-less LDO regulator proposed in this study achieves the transient response improved by applying body technique to the pass transistor, thereby provides the high areal efficiency and excellent current driving capability, and shows the improved ESD robustness characteristics. Also, the proposed ESD protection device based on due to the SCR (Silicon Control Rectifier) built into the output node and the power line. As a result, it was confirmed that the transient response characteristics of the proposed LDO regulator were improved and free space could be secured by applying the body technique of the pass transistor. The operating conditions of the proposed LDO regulator were set as an input voltage varying from 3.3V to 4.5V, a maximum load current of 200mA, and the output voltage of 3V. As a result of the measurement, when the load current was 200mA, the voltage was found to be 23mV in the undershoot state and 29mV in the overshoot state. In addition, the ESD robustness characteristic of HBM is secured at 8kV or higher.

A Novel DTSCR With Embedded MOS and Island Diodes for ESD Protection of High-Speed ICs

A novel diode-triggered silicon-controlled rectifier with embedded MOS and island diodes (DTSCR-EMOS-ID) is proposed and investigated. The DTSCR-EMOS-ID was fabricated in 0.18-μm and 22-nm CMOS processes for verifying the process transplantation. The fabricated DTSCR-EMOS-ID presents a low trigger voltage of 1.3 V, a small turn-on resistance of 8 mΩ/μm and a small parasitic capacitance of 43 fF. Meanwhile, the effective failure current and response time of DTSCR-EMOS-ID are optimized to 4.3 A and 3.6 ns, respectively. The DTSCR-EMOS-ID shows much better ESD performance than the conventional LVTSCR and DTSCR fabricated in the same process, which can be attributed to the diode triggering, gate coupling and large injection effects. Moreover, the TCAD simulation results of DTSCR-EMOS-ID agree well with the transmission line pulse testing results, further confirming that the proposed DTSCR-EMOS-ID can be widely used as an effective ESD protection device for high-speed ICs, without the limitation of the fabrication process.

Novel ESD Compact Modeling Methodology Using Machine Learning Techniques for Snapback and Non-Snapback ESD Devices

Novel ESD compact modeling methodology using machine learning techniques is proposed for the first time in this paper. ESD compact modeling for snapback and non-snapback ESD protection devices are discussed. Comparisons between conventional, novel fitting methodology and different machine learning models are discussed. The advantages of this novel methodology are introduced and methods to further improve the model accuracy are also discussed.

The Influence of N-Type Buried Layer on SCR ESD Protection Devices

This article investigates the effect of N-type buried layer (NBL) on the holding voltage and failure current of conventional low voltage triggered silicon-controlled rectifier (LVTSCR) and conventional dual directional silicon-controlled rectifier (DDSCR) devices. LVTSCR and DDSCR with N-type buried layer are fabricated on a 0.18- $\mu \text{m}$ Bipolar CMOS DMOS (BCD) technology. In order to verify and predict the effect of N-type buried layer on the characteristics of ESD protection devices, a transmission line pulse (TLP) testing system and a 2-dimension device simulation platform have been used in this work. According to the measurement results, the holding voltage ( ${\mathrm{ V}}_{\mathrm{ h}}$ ) and failure current ( ${\mathrm{ I}}_{\mathrm{ t2}}$ ) of the LVTSCR and DDSCR can be drastically improved by adding N-type buried layer.

Silicon Controlled Rectifier Based Partially Depleted SOI ESD Protection Device for High Voltage Application

Silicon Controlled Rectifier Based Partially Depleted SOI ESD Protection Device for High Voltage Application

Design of a novel high holding voltage LVTSCR with embedded clamping diode**Project supported by the National Natural Science Foundation of China (Grant No. 61504049) and the China Postdoctoral Science Foundation (Grant No. 2016M600361).

In order to reduce the latch-up risk of the traditional low-voltage-triggered silicon controlled rectifier (LVTSCR), a novel LVTSCR with embedded clamping diode (DC-LVTSCR) is proposed and verified in a 0.18-μm CMOS process. By embedding a p+ implant region into the drain of NMOS in the traditional LVTSCR, a reversed Zener diode is formed by the p+ implant region and the n+ bridge, which helps to improve the holding voltage and decrease the snapback region. The physical mechanisms of the LVTSCR and DC-LVTSCR are investigated in detail by transmission line pulse (TLP) tests and TCAD simulations. The TLP test results show that, compared with the traditional LVTSCR, the DC-LVTSCR exhibits a higher holding voltage of 6.2 V due to the embedded clamping diode. By further optimizing a key parameter of the DC-LVTSCR, the holding voltage can be effectively increased to 8.7 V. Therefore, the DC-LVTSCR is a promising ESD protection device for circuits with the operation voltage of 5.5–7 V.

A Fabrication of 4H-Silicon Carbide Based-Lateral SCR for ESD Protection Device

A Fabrication of 4H-Silicon Carbide Based-Lateral SCR for ESD Protection Device

Robustness of PIN Limiter Diodes to an ESD Event Based on VF-TLP Characterization

PIN limiter diodes are primarily used for protection from excess RF power in RF circuits. These diodes are positioned onboard at the I/O lines of the RF circuits. If an ESD event occurs, the first line of protection is offered by the PIN limiter diode. The main questions addressed in this letter are: Can the PIN limiter diode protect the RF circuit against ESD? If yes, then what is their ESD robustness? How do they compare against the standard ESD protection TVS diodes? This knowledge can guide the reader to understand whether or not the PIN limiter diode can help prevent ESD damage. The robustness of the diodes is investigated experimentally using a very fast transmission line pulse tester with a 10 ns pulse width and about 300–400 ps rise time. These diodes are tested for their withstand current, turn-on time at 1 A current, turn-on voltage, voltage clamp at 1 A current, capacitance, signal bandwidth, and effective package inductance. These diode parameters are essential in quantifying the component-level response of a device under test. This letter shows that the PIN limiter diodes are not a suitable replacement for the TVS diodes as an intentional ESD protection device. In case an ESD event occurs, these diodes are robust to ESD current levels up to 2.5-9 A and offer limited protection. They may effectively complement the TVS protection by offering a fast turn-on time and protection up to a certain ESD level, after which the (slower) TVS takes over.

A Comparison Study of Diode-String ESD Clamps for CMOS Input Protection

Based on 2-D device simulations and mixed-mode transient simulations, DC and transient discharge characteristics of a usual diode string utilizing a standard CMOS process, and a diode string utilizing a triple-well CMOS process, which can serve as an essential VDD-VSS clamp device for CMOS input ESD protection were compared. Transient discharge characteristics including peak voltages developed across gates oxides of transistors in input buffers, lattice heating inside ESD protection devices, and ratios of discharge current components at its peak inside the diode-string clamp were compared. DC standby current levels added per each input pad structure, which are the critical parameters determining usefulness of the devices, were also compared. We showed that the diode-string devices in comparison can serve successfully as a VDD-VSS clamp device for ESD protection by virtue of the dominant pnpn thyristor-related conduction mechanisms. Optimization of design parameters including anode-cathode contact spacing in each diode in the string, device width of the diode string, and number of diodes in the diode string was performed to present transient discharge and DC characteristics of some recommendable design examples, which can serve as a guideline in designing diode-string clamp devices.

A Study on SCR-Based ESD Protection Device with Improved Robustness Using Stack Technology

A Study on SCR-Based ESD Protection Device with Improved Robustness Using Stack Technology

Engineering ESD Robust LDMOS SCR Devices in FinFET Technology

A robust FinFET silicon-controlled rectifier (SCR) LDMOS ESD protection device is developed. Replacing the drain contact implant to the P+ implant from N+ implant creates an SCR inside the LDMOS and when the N+ contact is removed a Schottky SCR LDMOS is created. The ESD performance of the baseline FinFET LDMOS is Zero, while that of the SCR LDMOS is 9.2 mA/ $\mu {\mathrm{ m}}$ and Schottky SCR is 4.6 mA/ $\mu \text{m}$ respectively.

Analysis of SCR Based ESD Protection Device with Optimized Low Trigger Voltage for Low Trigger Voltage Applications

Analysis of SCR Based ESD Protection Device with Optimized Low Trigger Voltage for Low Trigger Voltage Applications