Equalizer Architecture Research Articles

An Interleaved Equalization Architecture with Self-Learning Fuzzy Logic Control for Series-Connected Battery Strings

This paper proposes an interleaved equalization architecture for series-connected lithium-ion battery strings, which can deliver energy from a battery module to the cells in the next adjacent battery module, resulting in an enhancement of the equalization current and efficiency. Particularly, the global equalization is achieved without the need of additional stage circuits to balance among modules, leading to a small size and low cost. A two-module equalizer based on resonant LC converter and buck converter with soft switching is implemented to verify the validity of the proposed interleaved architecture. Furthermore, a self-learning fuzzy logic control (SLFLC) algorithm is employed to online regulate the equalization period based on the voltage difference among cells and the cell voltage, not only greatly abbreviating the balancing time but also effectively preventing overequalization. The SLFLC has the outstanding advantages of high balancing precision, easy implementation, and strong robustness. Experimental results demonstrate that the proposed equalizer has good balancing performances with soft switching and high efficiency, and achieves zero-voltage gap among cells. Moreover, the proposed SLFLC algorithm abridges the total equalization time by about 27%, and reduces the equalization cycles by about 59% compared with the traditional control algorithm.

A 1.62–5.4-Gb/s Receiver for DisplayPort Version 1.2a With Adaptive Equalization and Referenceless Frequency Acquisition Techniques

We present a 1.62–5.4-Gb/s receiver for DisplayPort version 1.2a and propose an adaptive equalizer (EQ) with a peak-level comparison technique for eye measurement. A single comparator and an up/down unmatched-current charge pump are used to realize a simpler EQ architecture with low power dissipation. A referenceless frequency acquisition technique is also proposed. A time-to-digital converter-based pulsewidth detector supports the referenceless frequency acquisition within the range of 1.62–5.4 Gb/s. An XOR-gate-embedded charge pump and a half-rate linear phase detector were used to improve the jitter tolerance (JTOL) performance. The measured eye opening of the proposed EQ at 5.4 Gb/s was 0.68 UI with a −20-dB loss channel. The proposed receiver passed all the JTOL tests of the DisplayPort compliance specification version 1.2b. The power consumption of the receiver was 36.8 mW at 5.4 Gb/s. The receiver occupied a core area of 0.265 mm2 using 65-nm CMOS process technology.

An Efficient Distributed Arithmetic-Based Realization of the Decision Feedback Equalizer

A distributed arithmetic (DA)-based decision feedback equalizer architecture for IEEE 802.11b PHY scenarios is presented. As the transmission data rate increases, the hardware complexity of the decision feedback equalizer increases due to requirement for large number of taps in feed forward and feedback filters. DA, an efficient technique that uses memories for the computation of inner product of two vectors, has been used since DA-based realization of filters can lead to great computational savings. For higher-order filters, the memory-size requirement in DA would be high, and so ROM decomposition has been employed. The speed is further increased by employing digit-serial input operation. Two architectures have been presented, namely the direct-memory architecture and reduced-memory architecture where the later is derived using the former. A third architecture has also been presented where the offset-binary coding scheme is employed along with the ROM decomposition and digit-serial variants of DA. Synthesis results on Altera Cyclone III EP3C55F484C6 FPGA show that the proposed DA-based implementations are free of hardware multipliers and use less number of hardware resources compared to the multiply-and-accumulate-based implementation.

MIMO equalization optimized for baud rate clock recovery in coherent 112 Gbit/sec DP-QPSK metro systems

A novel MIMO equalization architecture optimized for baud rate clock recovery (BCR-MIMO) in coherent 112Gbit/sec dual polarization quadrature phase shift keying (DP-QPSK) metro systems is proposed. This architecture is designed to decouple between multiple-input-multiple-output (MIMO) equalization and clock recovery (CR) loops, avoiding the interaction between them. The decoupling between the two loops is achieved, while maintaining similar MIMO equalizer performance, as compared to the butterfly-structured equalizer.

A 12.4-mW 4.5-Gb/s Receiver With Majority-Voting 1-Tap Speculative DFE in 0.13- $\mu\hbox{m}$ CMOS

This brief presents a majority-voting 1-tap speculative decision-feedback equalization (DFE) architecture wherein the current-mode-logic (CML) selector after the slicers is replaced with a CML majority voter with two instead of three transistors in the stack, thereby resulting in improved speed and increased voltage headroom (or lower supply voltage operation). Compared with the traditional CML selector, the majority voter shows around 50% delay reduction at the same bias conditions and 25% reduction in supply. A receiver with the proposed majority-voting DFE is implemented in 0.13- μm CMOS process. With the DFE enabled, the receiver is able to equalize a 20-in channel over an FR4 board with 22-dB Nyquist loss at 4.5 Gb/s. The whole receiver core occupies 0.14 mm2 and consumes 12.4 mW.

A Design Methodology for Power Efficiency Optimization of High-Speed Equalized-Electrical I/O Architectures

Both power efficiency and per-channel data rates of high-speed input/output (I/O) links must be improved in order to support future inter-chip bandwidth demand. In order to scale data rates over band-limited channels, various types of equalization circuitry are used to compensate for frequency-dependent loss. However, this additional complexity introduces power and area costs, requiring selection of an appropriate I/O equalization architecture in order to comply with system power budgets. This paper presents a design flow for power optimization of high-speed electrical links at a given data rate, channel type, and process technology node, which couples statistical link analysis techniques with circuit power estimates based on normalized transistor parameters extracted with a constant current density methodology. The design framework selects the optimum equalization architecture, circuit logic style (CMOS versus current-mode logic), and transmit output swing for minimum I/O power. Analysis shows that low loss channel characteristics and minimal circuit complexity, together with scaling of transmitter output swing allows excellent power efficiency at high data rates.

An Asymptotic Approach to Parallel Equalization of Filter Bank Based Multicarrier Signals

A novel equalization structure for filter bank based multicarrier (FBMC) based modulations is proposed in this paper. The equalizer architecture is derived by assuming that the number of carriers is asymptotically large, and it consists of multiple parallel stages that are linearly combined on a per-subcarrier basis. The traditional single-tap per-subcarrier equalizer is obtained as a special case of the proposed architecture when the number of stages is fixed to one. An analytical characterization of the output signal to noise plus distortion ratio is provided, which can be used in practice to fix the number of parallel stages of the equalizer in order to obtain a certain performance level at the minimum complexity. Both simulations and analytical predictions indicate that high performance gains can be obtained with respect to more conventional FBMC equalization approaches. Furthermore, the proposed architecture is also shown to present important advantages in terms of computational complexity when compared with classical FBMC equalization architectures.

A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

This paper presents an improved decision feedforward equalizer (DFFE) for high speed receivers in the presence of highly dispersive channels. This decision-aided equalizer technique has been recently proposed for multigigabit communication receivers, where the use of parallel processing is mandatory. Well-known parallel architectures for the typical decision feedback equalizer (DFE) have a complexity that grows exponentially with the channel memory. Instead, the new DFFE avoids that exponential increase in complexity by using tentative decisions to cancel iteratively the intersymbol interference (ISI). Here, we demostrate that the DFFE not only allows to obtain a similar performance to the typical DFE but it also reduces the compelxity in channels with large memory. Additionally, we propose a theoretical approximation for the error probability in each iteration. In fact, when the number of iteration increases, the error probability in the DFFE tends to approach the DFE. These benefits make the DFFE an excellent choice for the next generation of high-speed receivers.

Channel equalization using quasi type-2 fuzzy strategies

This paper presents a proposal for channel equalization of non-linear time varying communication channels that uses strategies based on quasi type-2 fuzzy sets. Both triangular and trapezoidal quasi type-2 fuzzy equalizers are designed by means of an incremental design approach. A comparative experimental study among several fuzzy equalization architectures is carried out, showing that the equalizer based on trapezoidal quasi type-2 fuzzy sets exhibits the best performance for low and medium levels of uncertainty. The results of this work also suggest that high order fuzzy sets make the equalization process more robust to the variability of the communications channel.

Decision Feedback Equalizer Architectures With Multiple Continuous-Time Infinite Impulse Response Filters

Decision feedback equalizer (DFE) architectures with varying numbers of discrete-time taps and continuous-time infinite impulse response (IIR) filters are compared for use in typical wireline channels. In each case, the DFE coefficients are optimized to minimize a cost function that equally weights both jitter and vertical eye opening. Even when some reflections are present (e.g., backplane channels) continuous-time IIR taps can be effective if their filter coefficients are properly optimized. Using a DFE architecture with only two IIR filters provides adequate results for both a 26-dB loss coax cable and a 16 FR-4 backplane channel at 10 Gb/s while keeping the DFE complexity low. Furthermore, the implementation and experimental results of a DFE with multiple (three) IIR filters is reported. Fabricated in a 0.13 μm CMOS process, the DFE consumes 17.3 mW from a 1.2 V supply. A bit error rate (BER) of 10-12 was achieved at a data rate of 3.7 Gb/s.

Soft-Decision-Driven Channel Estimation for Pipelined Turbo Receivers

We consider channel estimation specific to turbo equalization for multiple-input multiple-output (MIMO) wireless communication. We develop a soft-decision-driven sequential algorithm geared to the pipelined turbo equalizer architecture operating on orthogonal frequency division multiplexing (OFDM) symbols. One interesting feature of the pipelined turbo equalizer is that multiple soft-decisions become available at various processing stages. A tricky issue is that these multiple decisions from different pipeline stages have varying levels of reliability. This paper establishes an effective strategy for the channel estimator to track the target channel, while dealing with observation sets with different qualities. The resulting algorithm is basically a linear sequential estimation algorithm and, as such, is Kalman-based in nature. The main difference here, however, is that the proposed algorithm employs puncturing on observation samples to effectively deal with the inherent correlation among the multiple demapper/decoder module outputs that cannot easily be removed by the traditional innovations approach. The proposed algorithm continuously monitors the quality of the feedback decisions and incorporates it in the channel estimation process. The proposed channel estimation scheme shows clear performance advantages relative to existing channel estimation techniques.

A Virtual-ADC Digital Background Calibration Technique for Multistage A/D Conversion

A nonlinear adaptive digital calibration technique for multistage analog-to-digital converters (ADCs) is presented. The approach is derived from a replica-path scaling principle inspired by the parallel-ADC equalization architecture. The treatment of residue gain nonlinearities leads to potentially significant power savings for a simple modification of the first ADC stage. The design tradeoffs involved in this technique, particularly a band-limited interpolator employed, are discussed in detail. Computer simulations demonstrate signal-to-noise-plus-distortion-ratio and spurious-free-dynamic-range improvements from 40 to 90 dB and 45 to more than 100 dB, respectively, for a 15-bit pipelined ADC.

Design considerations for high-data-rate chip interconnect systems

Over the past decade, data rates for electrical interconnects in interchip communications systems have experienced a dramatic increase from <;1 Gb/s to 10 Gb/s and beyond to keep up with ever increasing demands for more I/O bandwidth from modern high-capacity storage, networking, and data processing systems. This article presents an overview of the high-data-rate chip interconnect design space, including a short description of the channel, line equalization architecture, and design considerations for key I/O core subsystems realized in nanoscale CMOS technology.

A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer

This paper presents the design of a 1 Gb/s 5-tap T/2 fractionally-spaced equalizer. The T/2 delay lines are based on third-order linear-phase double terminated sections that offer a tunable group delay of 500 ps with less than 10% ripple and a 3 dB bandwidth greater than 600 MHz. Furthermore, the equalizer architecture introduces a broadband summing circuit using a transimpedance I/V converter that increases the bandwidth by a factor of 3.6 over a conventional resistive loaded analog adder. The topology's performance is demonstrated in the equalization of 1 Gb/s binary data through CAT5e twisted-pair cables for up to 23 meters. The vertical eye-opening increases from 0% to 58%. Implemented in CMOS 0.35 mum, the transversal equalizer occupies an area of 26 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 32 mA.

Implementation of a noninvasive data encryption technique based on a free-space spectral phase scrambling scheme

We investigate how to scale a free-space wavelength blocker to implement a spectral phase scrambling system to secure high data rate optical transmissions within a wavelength division multiplexing optical network. This technique belongs to the optical code-division multiple access family, and its implementation can be carried out using a free-space pulse shaping system based, for instance, on a wavelength blocker or spectral equalizer architectures. After a brief recall of the encryption principle, a model of the optical system is given, and we discuss the impact of phase distribution and the scrambling mask used to encrypt the data on penalty sources. We emphasize the importance of correctly choosing certain geometrical parameters, such as the beam waist in the spectral plane and the mask fill factor. The tolerance of this solution with respect to mask positioning errors is then investigated, and we finally discuss how such a solution could be implemented using existing devices, such as a wavelength blocker, for security applications without inducing additional system penalties.

Adaptation of turbo coding and equalization in turbo equalization for time-varying and frequency-selective channels

A number of authors have sought to combine equalization and decoding in an iterative system in order to reduce the effects of frequency and temporal dispersiveness of time-varying frequency-selective channels. In the recent literature, several architectures based on these iterative systems have been proposed. One can note architectures which combine a maximum a posteriori (MAP) equalizer and decoder, architectures formed by an interference canceller and MAP decoder, architectures implementing a decision feedback equalizer and a MAP decoder, etc. Most of these architectures require accurate channel estimation to adapt the equalizer filters or to execute the MAP equalizers. This article presents a turbo equalizer architecture for time-varying frequency-selective channels without channel estimators. The proposed turbo equalizer consists of an interference canceller in direct-adaptation mode and a turbo decoder. In order to reduce noise correlation, the addition of a transverse filter to the interference-canceller architecture is proposed. The reliability factor for variable time-varying frequency-selective channels is also redefined in order to improve the performance of the turbo decoder. The architecture of the proposed turbo equalizer reduces considerably the effects of frequency and temporal dispersiveness of time-varying frequency-selective channels depending on the normalized Doppler frequency range.

Structured Parallel Architecture for Displacement MIMO Kalman Equalizer in CDMA Systems

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A reduced complexity MIMO Kalman equalizer architecture is proposed in this brief by jointly considering the displacement structure and the block-Toeplitz structure. Numerical matrix–matrix multiplications with <formula formulatype="inline"> <tex>${\cal O}(F^{3})$</tex></formula> complexity are eliminated by simple data loading process, where <formula formulatype="inline"><tex>$F$</tex></formula> is the spreading factor. Finally, an iterative Conjugate-Gradient based algorithm is proposed to avoid the inverse of the Hermitian symmetric innovation covariance matrix in Kalman gain processor. The proposed architecture not only reduces the numerical complexity from <formula formulatype="inline"><tex>${\cal O}(F^{2})$</tex> </formula> to <formula formulatype="inline"><tex>${\cal O}(F\log_{2}F)$</tex> </formula> per chip, but also facilitates the parallel and pipelined VLSI implementation in real-time processing. </para>

An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI) of size (NF × NF) with O((NF)3) complexity to some FFT operations with O(NFlog2(F)) complexity and the inverse of some (N × N) submatrices. We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the (4 × 4) high-order receiver from partitioned (2 × 2) submatrices. This leads to more parallel VLSI design with 3 × further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity trade-off. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.

Adaptive MIMO decision feedback equalization for receivers with time-varying channels

In an attempt to reduce the computational complexity of vertical Bell Labs layered space time (V-BLAST) processing with time-varying channels, an efficient adaptive receiver is developed based on the generalized decision feedback equalizer (GDFE) architecture. The proposed receiver updates the filter weight vectors and detection order using a recursive least squares (RLS)-based time- and order-update algorithm. The convergence of the algorithm is examined by analysis and simulation, and it is shown that the proposed adaptive technique is considerably simpler to implement than a V-BLAST processor with channel tracking, yet the performances are almost comparable.

Equalizer Architectures for 40-Gb/s Optical Systems Limited by Polarization-Mode Dispersion

An analysis of first-order polarization-mode dispersion (PMD) effects in a 40-Gb/s optical system is used to compare different electronic equalizer architectures as potential PMD compensators. Both linear and nonlinear equalizers are considered employing symbol-spaced and fractionally-spaced taps. It is found that a decision feedback equalizer consisting of a 3-tap symbol-spaced feedforward equalizer and a 1-tap feedback equalizer effectively eliminates PMD as the dominant length-limiting factor in most 40-Gb/s optical systems. Such an equalizer would entail less complexity than several previously reported electronic PMD compensators.