Equalizer Architecture Research Articles

Dual-Layer Equalization Architecture for Antimisalignment Capability Enhancement in Multiple-Receiver-Based WPT Equalizer

Dual-Layer Equalization Architecture for Antimisalignment Capability Enhancement in Multiple-Receiver-Based WPT Equalizer

Channel Operating Margin Exploration as a Complementary Transceiver Circuit Design Tool for 25 Gbps PAM4 Serial Links

The design of high-speed serial links continues to attract the attention of the electronics industry due to the steady development of different telecommunications standards, generating a constantly growing data rate and new modulation schemes. However, conventional certification metrics can lead to sub-optimal transmit (Tx) and receive (Rx) circuit designs. Therefore, the Ethernet standard IEEE 802.3bj introduced a more effective evaluation method called channel operating margin (COM) to explore the design space at an early stage. Although the advantages of COM have been discussed in the literature and only a few works explore its potential as a backplane design tool, there are no reports on the use of COM as a complementary design tool for transceiver circuits. This work studies the use of COM as a complementary tool for transceiver design. COM performance is evaluated for four 100GBASE-KP4 backplanes and different equalization architectures. The impact of the metric and the challenges associated with incorporating new equalization structures into the COM flow are discussed. The results reveal a conventional Tx-Rx architecture that exceeds the COM threshold and an alternative one that improves the opening of the eye diagram but does not exceed the threshold.

OF-FSE: An Efficient Adaptive Equalization for QAM-Based UAV Modulation Systems

Quadrature amplitude modulation (QAM) is one of the essential components of unmanned 1 aerial vehicle (UAV) communications. However, the output signal accuracy of QAM deteriorates dramatically and even collapses in the case of UAVs in a harsh channel environment. This is due to the fractionally spaced equalization based on the multi-modulus blind equalization algorithm being implemented prior to carrier synchronization in QAM-based UAV modulation systems. The carrier frequency offset from the harsh channel signal thus contributes to the significantly degraded performance of MMA by suffering the fractionally spaced equalization. Therefore, in this paper, a novel offset feedback fractionally spaced equalization architecture for UAVs to eliminate the carrier frequency offset is first proposed. In this architecture, the carrier frequency offset allows estimated and incorporation into the input signal of fractionally spaced equalization to compensate for the offset. Moreover, a new multi-modulus decision-directed algorithm is presented for the novel architecture to improve the received signal accuracy of UAVs further. It enables adaptive optimization of the convergence process in accordance with the dynamic UAV communication environment employing the multi-modulus blind equalization algorithm and decision-directed blind equalization algorithm (MDD). Simulation results demonstrate the effectiveness of the OF-FSE framework in enabling the QAM-based UAV modulation systems operation in harsh channel scenarios. Moreover, the performance of the presented new MDD algorithm compared with baseline approaches is also confirmed.

Modularized Equalization Architecture With Transformer-Based Integrating Voltage Equalizer for the Series-Connected Battery Pack in Electric Bicycles

Modularized Equalization Architecture With Transformer-Based Integrating Voltage Equalizer for the Series-Connected Battery Pack in Electric Bicycles

Asynchronous Sampling-Based Hybrid Equalizer

An equalizer architecture based on asynchronous sampling is described. The circuit implementation is a hybrid feed-forward equalizer (FFE) using three digital postcursor taps realized via level-crossing samplers (LCSs) and inverter-based delays. Utilizing a current mode logic (CML)-based summer stage, an analog main tap and digital postcursor taps are combined into an inductively tuned resistor load. With a 0.67-mV-rms simulated output-referred noise, the FFE has better noise performance than a conventional continuous-time linear equalizer (CTLE) and a slicer/latch-based decision feedback equalizer (DFE) circuit. Moreover, it exhibits very good linearity and group delay performance suitable for an equalizer. Using inverter-based delays enables area efficiency as well as the capability to tune the delay across process voltage and temperature (PVT) variations. Since the FFE is an event-driven combinational logic based on the incoming data, it does not require synchronous sampling coming from a high-speed clock and data recovery (CDR), and it is advantageous for high-speed and multirate operation as its power consumption scales with the data rate. Fabricated in 40-nm CMOS technology, the hybrid FFE achieves energy per bit of 2.7 pJ/bit with a 20-dB Nyquist insertion loss link at the 28.57-Gb/s nonreturn to zero (NRZ) data rate.

Hardware-Efficient Duobinary Neural Network Equalizers for 800 Gb/s IM/DD PAM4 Transmission Over 10 km SSMF

In this article, we discuss challenges and options for scaling IM/DD transceivers towards 800Gbps. Our focus is CWDM4 PAM4 transmission and our target distance is 10km in O-band, which is a most urgent use case for next generation optical short reach systems like data centre interconnects and networks. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">At this reach and rate, chromatic dispersion (CD) becomes the main challenge. Its mitigation is essential and primarily done with digital signal processing. State of the art techniques, however, make transceivers quickly too complex. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">We show upon measurement results how neural network equalization can meet Volterra equalization performance with 30% less hardware multiplier complexity. When also applying magnitude weight pruning, an additional 43% reduction is possible without performance loss across all CWDM4 lanes. If needed, an added MLSE stage can further push performance in both cases. <p xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">In any of these configurations, a key enabler against strong CD penalties is duobinary training, which is applicable to all feed-forward equalization architectures.

Adaptive parallel decision deep neural network for high-speed equalization.

The equalization plays a pivotal role in modern high-speed optical wire-line transmission. Taking advantage of the digital signal processing architecture, the deep neural network (DNN) is introduced to realize the feedback-free signaling, which has no processing speed ceiling due to the timing constraint on the feedback path. To save the hardware resource of a DNN equalizer, a parallel decision DNN is proposed in this paper. By replacing the soft-max decision layer with hard decision layer, multi-symbol can be processed within one neural network. The neuron increment during parallelization is only linear with the layer count, rather than the neuron count in the case of duplication. The simulation results show that the optimized new architecture has competitive performance with the traditional 2-tap decision feedback equalizer architecture with 15-tap feed forward equalizer at a 28GBd, or even 56GBd, four-level pulse amplitude modulation signal with 30dB loss. And the training convergency of the proposed equalizer is much faster than its traditional counterpart. An adaptive mechanism of the network parameter based on forward error correction is also studied.

A low-power 1 Gb/s line driver with configurable pre-emphasis for lossy transmission lines

A line driver with configurable pre-emphasis is implemented in a 65 nm CMOS process. The driver utilizes a three-tap feed-forward equalization architecture. The relative delays between the taps are selectable in increments of 1/16th of the unit interval via an 8-stage delay-locked loop and digital interpolator. It is also possible to control the output amplitude and source impedance for each tap via a programmable array of eight source-series terminated drivers. The entire design consumes 9 mW from a 1.2 V supply at 1 Gb/s.

Bidirectional Constant Current String-to-Cell Battery Equalizer Based on L2C3 Resonant Topology

In battery equalization systems, equalization speed, control complexity, and length of energy flow path are the important figures of merits. This article presents a novel bidirectional L2C3 resonant converter in a unique equalizer architecture with constant balancing current and fixed frequency control. The constant balancing current can be customized to achieve a stable balancing speed. The common equalizer unit transfers power bidirectionally between the entire string and any single cell. Design considerations of L2C3-based bidirectional equalizer are analyzed in detail, which ensures zero-voltage switching among all <sc xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mosfets</small> during the equalization process. The circuit is designed with synchronous rectification using the first harmonics approximation. The key contributions of this article include: a new bidirectional resonant topology for battery equalization; bidirectional constant current balancing with open-loop control; simplified synchronous rectification. An equalizer prototype with four lithium-ion battery cells at a balancing current of 500 mA is built and tested. The L2C3 circuit operates at 200 kHz with a peak efficiency of 89.4% and 90.1% under two balancing modes. Experimental results show the proposed scheme exhibits outstanding balancing performance.

Soft-Demapping for Short Reach Optical Communication: A Comparison of Deep Neural Networks and Volterra Series

In optical fiber communication, optical and electrical components introduce nonlinearities, which require effective compensation to attain highest data rates. In particular, in short reach communication, components are the dominant source of nonlinearities. Volterra series are a popular countermeasure for receiver-side equalization of nonlinear component impairments and their memory effects. However, Volterra equalizer architectures are generally very complex. This article investigates soft deep neural network (DNN) architectures as an alternative for nonlinear equalization and soft-decision demapping. On coherent 92GBd dual polarization 64QAM back-to-back measurements performance and complexity is experimentally evaluated. The proposed bit-wise soft DNN equalizer (SDNNE) is compared to a 5th order Volterra equalizer at a 15% overhead forward error correction (FEC) limit. At equal performance, the computational complexity is reduced by 65%. At equal complexity, the performance is improved by 0.35 dB gain in optical signal-to-noise-ratio (OSNR).

An LLC-Based Battery Equalizer with Inherent Current Limitation

Automatic battery equalizers require no sensing circuits, which reduces their cost, size, and complexity. However, among existing methods, additional resistors or diodes are used in the balancing paths to ensure safe operation, which degrades the conversion efficiency and balancing speed. To overcome this problem, this article proposes an equalizer architecture based on the half-bridge LLC converter. The inherent current limitation characteristic of the proposed equalizer improves the balancing speed. High conversion efficiency is achieved due to the soft-switching operations of the switches. The circuit topology and working modes are presented first, then the features of voltage equalization, inherent current limitation, and soft-switching conditions are analyzed in detail. Finally, the proposed equalizer is validated by simulation and experiment.

Fuzzy Image Processing Based Architecture for Contrast Enhancement in Diabetic Retinopathy Images

Diabetic retinopathy” is damage to retina denotes one of the problems of diabetes which is a significant reason for visual infirmity and blindness. A comprehensive and routine eye check is important to early detection and rapid treatment. This study proposes a hardware system that can enhance the contrast in the diabetic retinopathy eye fundus images as a first step in different eye disease diagnoses. The fuzzy histogram equalization technique is proposed to increases the local contrast of Diabetic Retinopathy Images. First, a histogram construction hardware architecture for different image processing purposes has been built then modified with fuzzy techniques to create fuzzy histogram equalization architecture, which is used to enhance the original images. Both architectures are designed using a finite-state machine (FSM) technique and programmed with VHDL programming language. The first one is implemented using two (Spartan 3E-XC3S500 and Xilinx Artix-7 XC7A100T) kits, while the second architecture is implemented using (Spartan 3E-XC3S500) kit. The system consists also of a modified video graphics array (VGA) port to display the input and resulted images with a proper resolution. All the hardware outputs are compared to that results produce from MatLab for verification and the resulted images are tested by PSNR, MSE, ENTROPY ,and AMBE

An efficient adaptive equalization architecture for high-speed coherent PON systems

Algorithmic and architectural options and tradeoffs between performance and complexity/power dissipation are imperative to be considered in the transfer of coherent technology from long-haul transmission to passive optical network (PON) application. In this work, a novel low-complexity equalization architecture cascaded two frequency domain equalizers (FDEQs) and one 1-tap 2 × 2 butterfly equalizer is proposed targeting PON applications. FDEQ is designed to handle link chromatic dispersion (CD) and the imperfection of transceiver frequency response. The 1-tap 2 × 2 butterfly equalizer is introduced to realize polarization demultiplexing. A simplified FDEQ tap coefficient calculation method is designed. The performance of the proposed equalization architecture is experimentally verified by a 32-GBaud dual-polarization (DP) Nyquist-QPSK system over 20-km standard single-mode fiber (SSMF) transmission. With the proposed method, the number of hardened multipliers for field-programmable gate array (FPGA) realization is reduced by ∼90% compared with conventional 2 × 2 butterfly equalizer, at the expense of 0.5 dB receiver sensitivity.

Deep Neural Network Equalization for Optical Short Reach Communication

Nonlinear distortion has always been a challenge for optical communication due to the nonlinear transfer characteristics of the fiber itself. The next frontier for optical communication is a second type of nonlinearities, which results from optical and electrical components. They become the dominant nonlinearity for shorter reaches. The highest data rates cannot be achieved without effective compensation. A classical countermeasure is receiver-side equalization of nonlinear impairments and memory effects using Volterra series. However, such Volterra equalizers are architecturally complex and their parametrization can be numerical unstable. This contribution proposes an alternative nonlinear equalizer architecture based on machine learning. Its performance is evaluated experimentally on coherent 88 Gbaud dual polarization 16QAM 600 Gb/s back-to-back measurements. The proposed equalizers outperform Volterra and memory polynomial Volterra equalizers up to 6th orders at a target bit-error rate (BER) of 10 − 2 by 0.5 dB and 0.8 dB in optical signal-to-noise ratio (OSNR), respectively.

Statistical BER Analysis of Wireline Links With Non-Binary Linear Block Codes Subject to DFE Error Propagation

This paper presents a statistical model to accurately estimate post-FEC BER for high-speed wireline links using standard linear block codes, such as the RS(544,514,15) KP4 and RS(528,514,7) KR4 codes. A hierarchical approach is adopted to analyze the propagation of PAM-symbol and FEC-symbol errors through a two-layer Markov model. A series of techniques including state aggregation, time aggregation, state reduction, and dynamic programming are introduced making the time complexity to compute post-FEC BER below 10−15 reasonable. Error bounds associated with each method are found. The efficiency of the proposed model allows it to handle a larger state space, more DFE taps, and more sophisticated linear block codes than prior work. A 4-PAM 60 Gb/s wireline transceiver fabricated in a 7 nm FinFET technology is used as a test vehicle to validate this model. Measured data with two different channels reveals that the statistical model can properly predict the post-FEC error floor with standard FEC codes. While this paper demonstrates the method for capturing DFE error propagation, the method is general and can be applied to model other communication systems having memory effects. Moreover, our proposed model can be easily extended to higher-level PAM schemes and other advanced equalizer architectures to assist in making architectural choices for wireline transceivers.

Experimental Demonstration of the Tradeoff Between Chromatic Dispersion and Phase Noise Compensation in Optical FBMC/OQAM Communication Systems

Filterbank multicarrier based on offset quadrature amplitude modulation (FBMC/OQAM) is a promising candidate for optical fiber communication systems, thanks to its better time/frequency confinement compared to other multicarrier modulations. Among linear impairments, the compensation of fiber-induced chromatic dispersion (CD) and laser-induced phase noise (PN) in FBMC/OQAM systems induces a compromise in terms of the number of used subcarriers. Considering a fixed dedicated signal bandwidth, the number of subcarriers is expected to be large enough to allow a better frequency-domain CD compensation. On the other hand, it should be sufficiently small in order for the compensation of common phase error inherent to the PN to work properly. In this paper, we experimentally demonstrate the tradeoff between CD and PN compensation that we previously highlighted by simulations. More specifically, considering a 20-GHz FBMC/4-OQAM modulation and an aggregated laser linewidth of about 200 kHz, we show that the maximum transmission distance reaches 3100 km with nearly 512 active subcarriers and three-tap equalizers, when a maximum 1-dB optical signal-to-noise ratio penalty at a bit error rate of 3.8 × 10–3 can be tolerated. Moreover, we propose and validate a frame structure and an integrated synchronization/channel equalization architecture to implement a standalone demodulation system.

Modularized Equalization Architecture With Voltage Multiplier-Based Cell Equalizer and Switchless Switched Capacitor Converter-Based Module Equalizer for Series-Connected Electric Double-Layer Capacitors

This paper proposes a novel modular equalization architecture for series-connected electric double-layer capacitor (EDLC) modules, each consisting of multiple cells connected in series. Cell voltages in a module are equalized by an inductive voltage divider (IVD)-voltage multiplier (VM)-based cell equalizer, while module voltages are unified by switched capacitor converters (SCCs). Square wave voltages generated at switching nodes of the IVD-VM-based cell equalizers are utilized to drive the SCC-based module equalizers, realizing the switchless topology of SCC-based module equalizers. The required switch count of the proposed system can be halved compared to conventional systems, allowing simplified circuit. An experimental equalization test for three EDLC modules, each consisting of six cells in series, was performed from an initially voltage-imbalanced condition. Module and cell voltages were equalized at different rates, and the equalization performance of the proposed modular equalization system was successfully demonstrated.

An Efficient ANN Interference Cancelation for High Order Modulation over Rayleigh Fading Channel

High order modulation (HOM) presents a key challenge in increasing spectrum efficiency in 4G and upcoming 5G communication systems. In this paper, two non-linear adaptive equalizer techniques based on multilayer perceptron (MLP) and radial basis function (RBF) are designed and applied on HOM to optimize its performance despite its high sensitivity to noise and channel distortions. The artificial neural network’s (ANN) adaptive equalizer architectures and learning methods are simplified to avoid more complexity and to ensure greater speed in symbol decision making. They will be compared with the following popular adaptive filters: least mean square (LMS) and recursive least squares (RLS), in terms of bit error rate (BER) and minimum square error (MSE) with 16, 64, 128, 256, 512 and 1024 quadrature amplitude modulation (QAM). By that, this work will show the advantage that the MLP equalizer has, in most cases, over RBF and traditional linear equalizers.

Butterfly neural equalizer applied to optical communication systems with two-dimensional digital modulation.

This article aims to present, analyze and evaluate a new equalizer architecture, inspired by the butterfly equalizer used in optical communication, based on Artificial Neural Networks (ANN) of the Multi-Layer Perceptron (MLP) type for nonlinear systems with two-dimensional modulation named the Butterfly Neural Equalizer (NE-Butterfly). The NE-Butterfly is intended to equalize any channel that has real or complex taps, whether linear or nonlinear. Simulation results are presented for different types of nonlinear fiber optic channels with complex and real taps, also containing inter symbolic interference and additive noise. The results are compared with other neural equalizers in the literature with the objective of validating the performance of the NE-Butterfly, which stands out as having the overall best performance against the ones it was compared to.

Performance of ZF Linear Equalizers for Single Carrier Massive MIMO Uplink Systems

In this paper, we investigate the performance of the spatial-temporal zero-forcing linear equalizer architectures for a single-carrier Massive MIMO uplink system under frequency-selective fading environment. We establish relationships between the choosing equalizer length $D$ and the system performance in terms of system degrees of freedom and signal-to-interference plus noise ratio (SINR). We also present how system parameters (number of antennas $M$ and the transmit signal-to-noise ratio) impact the system performance differently for both single-cell systems and multi-cell systems with perfect and imperfect channel state information. Furthermore, we show that the probability density function (PDF) of the SINR can be accurately approximated as a Gamma distribution by using the moment matching method. Then, closed-form expressions of the ergodic rate and the outage probability are derived based on the PDF of the SINR.