Cu has been the metal of choice for interconnects in silicon microprocessors since the mid-1990s. The continuous scaling of these interconnects in CMOS technology has not only produced a challenge with respect to power consumption and computing performance, but also with respect to reliability. As the critical dimensions of interconnects are scaled towards, and then below the electron mean free path (EMFP) of Cu (39 nm at room temperature), the resistivity is found to increase. This increase, termed the resistivity size-effect, results in resistance scaling beyond Ohm’s law dimensional scaling and leads to even larger power consumption and further limits improvements in computing performance. The resistivity rise with decreasing dimension is a result of electron scattering at grain boundaries and surfaces (vs. phonons). Given that electron scattering from grain boundaries is the major contributor to the resistivity rise in nanoscale interconnects, there has been increasing interest in producing and evaluating epitaxial, single-crystal conductors absent of grain boundaries. In this presentation, epitaxial electrodeposition of Co, Ru and Cu at room-temperature is reviewed. The choice of seed layer for electrodeposition, the role of symmetry of the seed layer and the epitaxial orientation relationship of the electrodeposited film and the seed layer are discussed. In addition, the impact of underpotential deposition on film nucleation and growth morphology is examined. The effects of electrolyte, ion concentration and pH are also addressed. Potential pathways for implementation of epitaxial electrodeposition in back-end-of-line processing will be discussed.
Read full abstract