Entire Interconnect Research Articles

The impact of titanium alloying on altering nanomechanical properties and grain structures of sputter-deposited cobalt for electromigration reliability enhancement

Cobalt (Co) has recently become a highlighted on-chip interconnection material for advanced metallization scheme of microelectronic circuits. Here, electromigration behaviors of sputter-deposited Co and Co(Ti; 0.9 at%) interconnection lines embedded in Si are comparatively studied. These lines were annealed (500 °C/30 min) prior to further accelerated electromigration testing under high current densities in the range of 3 × 107–9 × 108 A cm−2. A collection of the obtained electromigration failure lifetimes, current scaling factors and activation energies confirms a noticeable enhancement in the electromigration reliability of the Co lines by the added Ti. Results by scanning transmission electron microscopy (STEM) and nanoscratch testing reveal that 3–5 nm-sized Ti crystallites are uniformly dispersed in the Co-interconnect matrix, effectively inhibiting Co grain growth, promoting the formation of nanotwinned Co and elevating film’s mechanical properties for ensuring the electromigration reliability. With deteriorated hardness and adhesion energy, reduced planar defects and many big grains all spanning transversely the entire interconnect line, Co is vulnerable to electromigration failures, also giving accelerated thermally-induced interfacial diffusion and chemical reactions with the surrounding Si, as proven by depth-profiling secondary spectrometry and STEM analysis.

Void-dynamics in nano-wires and the role of microstructure investigated via a multi-scale physics-based model

With scaling of nano-interconnect linewidth toward a 3 nm technology node, electromigration in copper nano-interconnects is becoming a major limitation. In this context, the increase of texture polycrystallinity plays a major role and necessitates better understanding of the impact of void dynamics and its interaction with texture at operating conditions. To this end, comprehensive, yet efficient, physics-based numerical models are warranted given that electromigration experiments at low operating temperatures are not feasible. Albeit, development of such models has been a challenge since it involves large length-scale discrepancy between features, i.e., from wire dimensions (hundreds of micrometers) down to grains and voids (tens of nano-meters and below) leading to substantial computational cost. To this end, in this study an efficient multi-scale physics-based electromigration modeling approach is demonstrated, where an experimentally calibrated Korhonen-type 1D model solves electromigration at the global scale (entire interconnect), and a 2D local model simulates void dynamics considering the impact of electron wind, void surface energy, and stress gradients. The role of copper texture, i.e., grain boundaries, grain orientation and anisotropic properties is thoroughly investigated. We demonstrate that by tailoring the copper grain structure, void behavior and thus resistance evolution of nanowires can be effectively controlled. Compared to wider interconnects, in scaled nanowires, surface energy is found to play a dominant role on void morphology compared to electron wind. Strong anisotropy of diffusivity of copper's FCC lattice fosters faceted morphologies and emergence of slit morphology during void transition through the polycrystalline texture. Bamboo segments are shown to effectively pin the voids migrating toward the cathode in cases with cobalt cap. In addition, voids migrating from low diffusivity to high diffusivity regions adopt a longitudinally elongated morphology, which can be detrimental in a down-stream operation mode.

$1.3~\mu $ m Optical Interconnect on Silicon: A Monolithic III-Nitride Nanowire Photonic Integrated Circuit

A feasible optical interconnect on a silicon complementary metal-oxide-semiconductor chip demands epitaxial growth and monolithic integration of diode lasers and optical detectors with guided wave components on a (001) Si wafer, with all the components preferably operating in the wavelength range of 1.3-1.55 μm at room temperature. It is also desirable for the fabrication technique to be relatively simple and reproducible. Techniques demonstrated in the past for having optically and electrically pumped GaAs and InP-based lasers on silicon include wafer bonding, selective area epitaxy, epitaxy on tilted substrates, and use of quantum dot or planar buffer layers. Here, we present a novel monolithic optical interconnect on a (001) Si substrate consisting of a III-nitride dot-in-nanowire array edge emitting diode laser and guided wave photodiode, with a planar SiO 2 /Si 3 N 4 dielectric waveguide in between. The active devices are realized with the same nanowire heterostructure by one-step epitaxy. The electronic properties of the InN dot-like nanostructures and mode confinement and propagation in the nanowire waveguides have been modeled. The laser, emitting at the desired wavelength of 1.3 μm, with threshold current ~350 mA for a device of dimension 50 μm × 2 mm, has been characterized in detail. The detector exhibits a responsivity ~0.1 A/W at 1.3 μm. Operation of the entire optical interconnect via the dielectric waveguide is demonstrated.

Electrothermal Transport in Carbon Nanostructures

An empirical model is developed that takes into account heat transport through the entire carbon nanofiber interconnect test structure and breakdown location. This electrothermal transport model elucidates observed current capacity behavior, and predicts variations in contact location with the support material. The resulting heat dissipation and current capacity are completely consistent with measurement data.

Electrothermal Analysis of Breakdown in Carbon Nanofiber Interconnects

To elucidate the observed current capacity behavior, a model is developed that takes into account heat transport through the entire carbon nanofiber interconnect test structure and breakdown location. The model also includes variations in contact location with the support material. The resulting predicted heat dissipation and current capacity are completely consistent with experimental data.

Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs

A model development methodology for complex shaped on-wafer interconnects is presented. The equivalent circuit of the entire interconnect is obtained by cascading basic subsegment models. The extracted parameters are formulated into empirical expressions. Thus, the proposed model can be easily incorporated with commercial electronic design automation (EDA) tools. The accuracy of the model is validated by the on-wafer measurements up to 20 GHz.

Innovative method for modelling tree structured interconnects

A new technique to generate macromodels of tree structured interconnects including the effect of inductances and frequency dependent per unit length parameters is presented. The proposed method allows the derivation of the exact transfer function of an interconnect tree with distributed RLC models. It presents some advantages over other techniques: first, it enables to easily incorporate frequency dependent phenomena such as skin effect and dielectric losses in a macromodel of the entire interconnect tree; second, a model order reduction can be efficiently performed at the level of each single interconnect, thus leading to a reduced-order model of the entire interconnect; third, the knowledge of all the poles of the tree is made possible by solving low-order algebraic equations at a reduced computational cost. The examples confirm that the proposed method is able to capture the physics of the interconnect trees, being accurate and efficient at the same time.

A Holistic Approach to Designing Energy-Efficient Cluster Interconnects

Designing energy-efficient clusters has recently become an important concern to make these systems economically attractive for many applications. Since the cluster interconnect is a major part of the system, the focus of this paper is to characterize and optimize the energy consumption in the entire interconnect. Using a cycle-accurate simulator of an InfiniBand Architecture (IBA) compliant interconnect fabric and actual designs of its components, we investigate the energy behavior on regular and irregular interconnects. The energy profile of the three major components (switches, network interface cards (NICs), and links) reveals that the links and switch buffers consume the major portion of the power budget. Hence, we focus on energy optimization of these two components. To minimize power in the links, first we investigate the dynamic voltage scaling (DVS) algorithm and then propose a novel dynamic link shutdown (DLS) technique. The DLS technique makes use of an appropriate adaptive routing algorithm to shut down the links intelligently. We also present an optimized buffer design for reducing leakage energy in 70nm technology. Our analysis on different networks reveals that, while DVS is an effective energy conservation technique, it incurs significant performance penalty at low to medium workload. Moreover, energy saving with DVS reduces as the buffer leakage current becomes significant with 70nm design. On the other hand, the proposed DLS technique can provide optimized performance-energy behavior (up to 40 percent energy savings with less than 5 percent performance degradation in the best case) for the cluster interconnects.

Migration-forced metal extrusion from passivated molybdenum disilicide interconnects

The incorporation of aluminium from contact pads during electromigration experiments with MoSi 2 interconnect lines was investigated. The experimental results prove that once incorporated into the lines, the atomic electrodiffusion of aluminium follows grain boundary paths through the via. In this work, we have isolated the effects of microstructure on the migration behavior. While in lines with a polygranular structure the Al-atoms followed the continuous grain boundary path along the length of the entire interconnect line and accumulated on the anode contact pad, lines with a near-bamboo grain structure showed aluminium extrusion through the liner of the capping layer. The dielectric cracking at discrete spots is the consequence of the build-up of compressive stress σ in front of large ‘near-bamboo’ grains, which is relieved by a positive mass flux to the surface of the interconnect line at ‘grain-boundary’ outlets, as soon as a yield value of σ is reached in front of a blocking grain.

In-Situ Electromigration Damage of Al Interconnect Lines and the Influence of Grain Orientation

AbstractIn this work the authors want to report some experiments concerning unpassivated Al interconnect lines of 8 and 1.4 microns width which have been damaged by in-situ electromigration in the SEM (temperature 230°C, current density 2 and 4×106 A/cm2, respectively). The wider line represents a polygrained structure with few blocking grains spanning the whole width, whereas the narrow line shows bamboo structure. Before electromigration, the local orientation and thus the position of all grain boundaries was mapped by EBSD technique along the entire interconnect line. During and after in-situ current loading in the SEM, the damaged sites were correlated with the grain boundary map to locate where the diffusion paths are situated most likely. It was found that not the deviation from <111> fibre texture, but the misorientation class of the grain boundaries is essential for the localization of the fatal defects.

Fully differential optical interconnections for high-speed digital systems

This work presents the design details and experimental results for a parallel optical link. The link is designed for connections within high-speed digital systems, specifically for board- and backplane-level interconnections. The link can contain as many fibers in parallel as technology permits. The unusual aspects of this interconnection system are that it is DC-coupled and uses fully differential inputs, two optical channels per signal, to achieve self-thresholding and noise immunity. A chip set consisting of a 2.5-Gb/s bipolar differential laser driver, a 800-Mb/s GaAs MSM (metal-semiconductor-metal) preamplifier array, a 800-Mb/s GaAs MSM preamplifier-postamplifier array, and a GaAs MSM preamplifier array in which each preamplifier has a different bandwidth varying from 300 Mb/s to 2 Gb/s has been designed, fabricated, and tested to serve as a vehicle for verifying the concept. Although the experimental testing of the entire interconnect system is not yet complete, the experimental studies presented show a bandwidth in excess of 800 MHz and excellent signal isolation between channels.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>