Enhancement Mode Operation Research Articles

(Invited) Power Electronic Devices Based on Al-Rich Aluminum Gallium Nitride

After decades of research, the wide-bandgap (WBG) semiconductors GaN and SiC are beginning to enjoy commercial success for power electronics applications. Both high breakdown voltage and low on-state resistance are important factors that have enabled improved performance and efficiency of power switching transistors based on these WBG semiconductors. However, truly dramatic improvements in power device performance for extreme applications are likely to require a new class of semiconductor materials with bandgaps greater than that of GaN (3.4 eV), the so-called “ultra” wide-bandgap (UWBG) semiconductors. The critical electric field (EC) affecting breakdown scales approximately as Eg 2.5 [1], making the UWBG semiconductors capable of extremely high voltage operation. In particular, Al-rich AlGaN alloys approaching AlN with its 6.2 eV bandgap have an estimated EC that may be nearly 5x that of GaN, and nearly 2x that of ß-Ga2O3, another UWBG material that is currently receiving increased research interest. Since the first report of an AlGaN-channel transistor [2], progress has been steady and an increasing number of approaches to realizing Al-rich devices have been evaluated. High electron mobility transistors have been realized at channel concentrations as high as 85% Al [3]. However, research into this material for power applications is in its early days, and many challenges remain to be addressed in epitaxial growth, defect physics, fundamental material properties, device processing, and how these relate to device design. This talk will describe Sandia National Laboratories’ efforts to develop Al-rich AlGaN into the material of choice for next-generation power electronics applications. Research will be motivated by comparing power switching figures of merit against ß-Ga2O3 and other UWBG semiconductors being considered for future power electronics applications. The latest results in AlGaN-channel HEMTs will be described, including improvements in current density, recent approaches to realizing enhancement-mode operation, and analysis of the device characteristics over a range of temperature and bias conditions. Details regarding ongoing work to optimize device performance for Al-rich AlGaN transistors will be presented in the talk and final proceedings paper. This work was supported by the Laboratory Directed Research and Development program at Sandia National Laboratories. Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. [1] R. J. Kaplar, et al., ECS J. Solid State Science and Technology, vol. 6, p. Q3061 (2017). [2] T. Nanjo, et al., Appl. Phys. Lett. 92, 263502 (2008). [3] A.G. Baca, et al., Appl. Phys. Lett. 109, 033509 (2016).

Vertical GaN-on-Si MOSFETs With Monolithically Integrated Freewheeling Schottky Barrier Diodes

We demonstrate for the first time the monolithic integration of vertical GaN MOSFETs with freewheeling Schottky barrier diodes (SBD), based on a 6.7- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> -thick n-p-n heterostructure grown on 6-inch silicon substrates by metal organic chemical vapor deposition. The anode of the SBD is integrated in the source pad of the MOSFET and the cathode is directly connected to the MOSFET drain through the bottom n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> -GaN layer, eliminating the need of any metal wire interconnection. This monolithic integration scheme offers reduced footprint, minimized parasitic components, and simplified packaging. The integrated MOSFET-SBD showed enhancement-mode operation with a threshold voltage of 3.9 V, an ON/ OFF ratio of over 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sup> and a dramatic improvement in reverse conduction, without degradation in on-state performance from the integration of the SBD. The integrated GaN-on-Si vertical SBD exhibited excellent performance, with a specific on-resistance of 1.6 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega \cdot $ </tex-math></inline-formula> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> , a turn-on voltage of 0.76 V, an ideality factor of 1.5, along with a breakdown voltage of 254 V.

Normally Off Vertical 3-D GaN Nanowire MOSFETs With Inverted &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;${p}$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-GaN Channel

This paper reports on the normally off GaN vertical MOSFETs based on nanowires (NWs) with an inverted p-GaN channel and a wrap-around-gate structure for the first time. Both inductively coupled plasma dry reactive-ion etching and wet-chemical etching were employed to fabricate the vertically aligned GaN NWs from epitaxial thin films with a specified doping profile. During the wet etching, the influence of p-doping on the NW morphology was investigated, and the results could be explained by the proposed model. In comparison with other c-axis NW transistors, an enhancement-mode (E-mode) operation with a superior threshold voltage ( $V_{{\text {th}}}$ ) of 2.5 V has been reached in the fabricated GaN MOSFETs. Furthermore, a high driving-current density of 101 kA/cm2 as well as a high ON-/OFF-current ratio of 109 was obtained in the NWs, predicting a potential approach toward future GaN electronics with vertical and smart architecture.

Polarization engineered enhancement mode GaN HEMT: Design and investigation

In this paper, we propose and perform the experimentally calibrated simulation of a novel structure of a GaN/AlGaN high electron mobility transistor (HEMT). The novelty of the structure is the realization of enhancement mode operation by employing polarization engineering approach. In the proposed polarization engineered HEMT (PE-HEMT) a buried Aluminum Nitride (AlN) box is employed in the GaN layer just below the gate. The AlN box creates a two-dimensional hole gas (2DHG) at the GaN/AlN interface, which creates a conduction band barrier in the path of the already existing two-dimensional electron gas (2DEG) at GaN/AlGaN. Therefore, there is no direct path between the source and drain regions at zero gate voltage due to the barrier created by AIN and the device is initially OFF, an enhancement mode operation. A two dimensional (2D) calibrated simulation study of proposed PE-HEMT shows that the device has a threshold voltage (Vth) of 2.3 V. The PE-HEMT also reduces the electron spillover and thus improves the breakdown voltage by 108% as compared to conventional HEMT. The thermal analysis of the GaN PE-HEMT shows that a hot zone occurs on the drain side gate edge. It has been observed that the drain current in the PE-HEMT structure can be improved by 157% by using AlN heat sink.

AlGaN/GaN High Electron Mobility Transistors with a p-Type GaN Cap Layer

In this work, AlGaN/GaN HEMTs with different types of p-GaN cap layers were fabricated and investigated. The p-GaN cap layer used in this study was for passivation study instead of forming enhancement-mode operation. The differences in p-GaN cap layers were Mg-doping concentration (1×1019 and 3×1019 cm-3) and thickness (5 and 8 nm). Device with p-GaN cap of 8-nm and Mg-doping of 3×1019 cm-3 showed the lowest gate leakage current, highest on/off current ratio (1.02×106), highest breakdown voltage and least current collapse characteristics.

Modelling the threshold voltage of p‐channel enhancement‐mode GaN heterostructure field‐effect transistors

p-Channel gallium nitride (GaN) metal–oxide–semiconductor heterostructure field-effect transistors utilising a polarisation induced two-dimensional hole gas operate inherently in depletion mode. The condition for their conversion to enhancement-mode operation is examined via analytical expressions for the threshold voltage and verified via technology computer-aided design (TCAD) simulations. Between the two heterostructures: (i) conventional GaN/aluminium GaN (AlGaN)/GaN and (ii) alternate AlGaN/GaN/AlGaN/GaN examined in this work, the authors demonstrate at higher threshold voltage (), the alternate heterostructure can potentially achieve a higher on-current by a factor of 2 of (), without degradation in the on–off-current ratio, expected ideally to be of the order of .

Nanoscale structural and chemical analysis of F-implanted enhancement-mode InAlN/GaN heterostructure field effect transistors

We investigate the impact of a fluorine plasma treatment used to obtain enhancement-mode operation on the structure and chemistry at the nanometer and atomic scales of an InAlN/GaN field effect transistor. The fluorine plasma treatment is successful in that enhancement mode operation is achieved with a +2.8 V threshold voltage. However, the InAlN barrier layers are observed to have been damaged by the fluorine treatment with their thickness being reduced by up to 50%. The treatment also led to oxygen incorporation within the InAlN barrier layers. Furthermore, even in the as-grown structure, Ga was unintentionally incorporated during the growth of the InAlN barrier. The impact of both the reduced barrier thickness and the incorporated Ga within the barrier on the transistor properties has been evaluated theoretically and compared to the experimentally determined two-dimensional electron gas density and threshold voltage of the transistor. For devices without fluorine treatment, the two-dimensional electron gas density is better predicted if the quaternary nature of the barrier is taken into account. For the fluorine treated device, not only the changes to the barrier layer thickness and composition, but also the fluorine doping needs to be considered to predict device performance. These studies reveal the factors influencing the performance of these specific transistor structures and highlight the strengths of the applied nanoscale characterisation techniques in revealing information relevant to device performance.

GaN-on-Si Quasi-Vertical Power MOSFETs

We demonstrate the first GaN vertical transistor on silicon, based on a 6.7- $\mu \text{m}$ -thick n-p-n heterostructure grown on 6-inch silicon substrate by metal organic chemical-vapor deposition. The devices consist of trench-gate quasi-vertical metal–oxide–semiconductor field-effect transistors with a 4- $\mu \text{m}$ -thick drift layer, exhibiting enhancement-mode operation with a threshold voltage of 6.3V and an ON/OFF ratio of over 108. A high OFF-state breakdown voltage of 645 V along with a specific ON-resistance of $6.8~\textsf {m}\Omega \cdot \textsf {cm}^{{\textsf {2}}}$ were achieved thanks to the high-quality 4- $\mu \text{m}$ -thick GaN drift layer, presenting a relatively low defect density and very high electron mobility (720 cm $^{{\textsf {2}}}/\textsf {V}\cdot \textsf {s}$ ). This excellent performance represents a major step toward the realization of high-performance GaN vertical power transistors on low-cost silicon substrates.

β-Ga2O3 Nanomembrane Negative Capacitance Field-Effect Transistors with Steep Subthreshold Slope for Wide Band Gap Logic Applications.

Steep-slope β-Ga2O3 nanomembrane negative capacitance field-effect transistors (NC-FETs) are demonstrated with ferroelectric hafnium zirconium oxide in the gate dielectric stack. Subthreshold slope less than 60 mV/dec at room temperature is obtained for both forward and reverse gate-voltage sweeps with a minimum value of 34.3 mV/dec at the reverse gate-voltage sweep and 53.1 mV/dec at the forward gate-voltage sweep at VDS = 0.5 V. Enhancement-mode operation with a threshold voltage of ∼0.4 V is achieved by tuning the thickness of the β-Ga2O3 membrane. Low hysteresis of less than 0.1 V is obtained. The steep-slope, low hysteresis, and enhancement-mode β-Ga2O3 NC-FETs are promising as an nFET candidate for future wide band gap complementary metal-oxide-semiconductor logic applications.

Noise characterization of enhancement-mode AlGaN graded barrier MIS-HEMT devices

This paper reports a systematic theoretical study on the microwave noise performance of graded AlGaN/GaN metal-insulator semiconductor high-electron mobility transistors (MIS-HEMTs) built on an Al2O3 substrate. The HfAlOx/AlGaN/GaN MIS-HEMT devices designed for this study show an outstanding small signal analog/RF and noise performance. The results on 1 μm gate length device show an enhancement mode operation with threshold voltage, VT = + 5.3 V, low drain leakage current, Ids,LL in the order of 1 × 10−9 A/mm along with high current gain cut-off frequency, fT of 17 GHz and maximum oscillation frequency fmax of 47 GHz at Vds = 10 V. The device IV and low-frequency noise estimation of the gate and drain noise spectral density and their correlation are evaluated using a Green's function method under different biasing conditions. The devices show a minimum noise figure (NFmin) of 1.053 dB in combination with equivalent noise resistance (Rn) of 23 Ω at 17 GHz, at Vgs = 6 V and Vds = 5 V which is relatively low and is suitable for broad-band low-noise amplifiers. This study shows that the graded AlGaN MIS-HEMT with HfAlOX gate insulator is appropriate for application requiring high-power and low-noise.

Design and simulation of a doping-less charge plasma based enhancement mode GaN MOSFET

In this work, we design and simulate a doping-less normally OFF/enhancement mode GaN based MOSFET. The novelty of the device is that it uses the charge plasma concept to induce n type charge plasma in an undoped GaN film, by employing metal electrodes, to realize source and drain regions of a GaN MOSFET. The proposed device is not a hetero-structure device, like the conventional GaN/AlGaN MOSFET and is hence more reliable and free from the hetero-epitaxial defects, inverse piezoelectric effects, and can have reduced leakage. Further, the proposed device can be fabricated at a reduced thermal budget as it does not possess any doped region. A two dimensional calibrated simulation study of the proposed device has revealed that it exhibits a threshold voltage of 1.4 V, large $$I_{\mathrm{ON}}/I_{\mathrm{OFF}}$$ ratio of $$10 ^{12}$$ , cutoff frequency ( $$f_\mathrm{T}$$ ) of 0.58 GHz, maximum oscillation frequency ( $$f_{\mathrm{max}}$$ ) of 3.2 GHz, transconductance ( $$g_{\mathrm{m}}$$ ) of 40 mS/mm and a breakdown voltage of 22 V (at $$L_\mathrm{GD}= 0$$ ). Further, the enhancement mode operation in the proposed device has been realized in a much easier way than that in the state of the art doping less AlGaN/GaN based devices. A process flow for the fabrication of the proposed device is also given.

Enhancement-Mode GaN MOS-HEMT with Quaternary InAlGaN-Barrier

The quaternary InAlGaN-barrier GaN MOS-HEMT (high-electron-mobility transistor) with enhancement mode operation was displayed as Vth=0.65V and the maximum drain current ~ 40 mA/mm at VDS=10V with LG=15μm and LGD=20μm. The measured rocking-curve and RSM (reciprocal space mapping) for epitaxial quality was confirmed the composition of the quaternary and analyzed the relaxation between InAlGaN-barrier and GaN Buffer layer. The surface roughness of InAlGaN was observed by AFM (Atomic force microscopy). The positive polarity of Vth was obtained with the gate lengths 3-30μm, and short channel effect was discussed.

Embedded gate CVD MoS2 microwave FETs

Recent studies have increased the cut off frequencies achievable by exfoliated MoS2 by employing a combination of channel length scaling and geometry modification. However, for industrial scale applications, the mechanical cleavage process is not scalable but, thus far, the same device improvements have not been realized on chemical vapor deposited MoS2. Here we use a gate-first process flow with an embedded gate geometry to fabricate short channel chemical vapor deposited MoS2 radio frequency transistors with a notable fT of 20 GHz and fmax of 11.4 GHz, and the largest high-field saturation velocity, vsat = 1.88 × 106 cm/s, in MoS2 reported so far. The gate-first approach, facilitated by cm-scale chemical vapor deposited MoS2, offers enhancement mode operation, ION/IOFF ratio of 108, and a transconductance (gm) of 70 μS/μm. The intrinsic fT (fmax) obtained here is 3X (2X) greater than previously reported top-gated chemical vapor deposited MoS2 radio frequency field-effect transistors. With as-measured S-parameters, we demonstrate the design of a GHz MoS2-based radio frequency amplifier. This amplifier has gain greater then 15 dB at 1.2 GHz, input return loss > 10 dB, bandwidth > 200 MHz, and DC power consumption of ~10 mW.

Use of a bilayer lattice-matched AlInGaN barrier for improving the channel carrier confinement of enhancement-mode AlInGaN/GaN hetero-structure field-effect transistors

A quaternary lattice-matched layer structure based on employing a bilayer barrier for improving the carrier confinement in the channel of enhancement-mode metal-face c-plane wurtzite AlInGaN/GaN hetero-structure field effect transistors (HFETs) is for the first time proposed. Using the commercial self-consistent Poisson-Schrödinger solver Nextnano, electronic properties of the proposed hetero-structure, including the sheet charge density and carrier confinement on the GaN side of the hetero-interface, are evaluated. Based on these evaluations, it is shown that while the proposed layer structure substantially improves the carrier confinement in the GaN channel layer, it also upholds the merits of employing a lattice-matched barrier towards achieving an enhancement-mode operation (i.e., in the absence of the piezoelectric effect). According to these simulations, in terms of maintaining the required positive threshold-voltage for the enhancement-mode operation, it is also shown that the proposed layer structure substantially outperforms the quaternary AlInGaN/GaN HFETs employing a thin AlN spacer layer.

DC and microwave characteristics of 20 nm T-gate InAlN/GaN high electron mobility transistor for high power RF applications

The DC and microwave characteristics of 20 nm gate length (Lg) InAlN/GaN High electron mobility transistor (HEMT) on SiC substrate with heavily doped source and drain region have investigated for both depletion mode (D-mode) and Enhancement mode (E-mode) operation using Synopsys TCAD tool. The simulation is performed at room temperature by using drift-diffusion model. The device having the features of recessed T - gate structure, InGaN back barrier and Al2O3 passivated device surface. The proposed novel Lg = 20 nm, W = 2 × 40 μm D-mode (E-mode) HEMT exhibited a peak drain current density (Idmax) of 2.7 (2.6) A/mm, transconductance (gm) of 1.04 (1.63) S/mm, current gain cut-off frequency (ft) of 310 (343) GHz and power gain cut-off frequency (fmax) of 364 (236) GHz. The measured carrier mobility (μ), sheet charge carrier density (ns) and breakdown voltage are 1580 (1615) cm2/V−s, 1.9 × 1013 (1.93) Cm−2 and 10.7 (12.8) V respectively. The superlatives of the proposed HEMTs are bewitching competitor for future sub-millimetre wave high power RF VLSI circuit applications.

Investigation of enhancement mode HfO2 insulated N-polarity GaN/InN/GaN/In0.9Al0.1N heterostructure MISHEMT for high-frequency applications

In this paper, we examined normally-OFF N-polar InN-channel Metal insulated semiconductor high-electron mobility transistors (MISHEMTs) device with a relaxed In0.9Al0.1N buffer layer. In addition, the enhancement-mode operation of the N-polar structure was investigated. The effect of scaling in N-polar MISHEMT, such as the dielectric and the channel thickness, alter the electrical behavior of the device. We have achieved a maximum drain current of 1.17A/mm, threshold voltage (VT) =0.728V, transconductance (gm) of 2.9Smm−1, high ION/IOFF current ratio of 3.23×103, lowest ON-state resistance (RON) of 0.41Ωmm and an intrinsic delay time (τ) of 1.456 Fs along with high-frequency performance with ft/ fmaxof 90GHz/109GHz and 180GHz/260GHz for TCH =0.5nm at Vds =0.5V and 1.0V. The numerically simulated results of highly confined GaN/InN/GaN/In0.9Al0.1N heterostructure MISHEMT exhibits outstanding potential as one of the possibility to replace presently used N-polar MISHEMTs for delivering high power density and frequency at RF/power amplifier applications.

Normally-Off AlGaN/GaN Mos-Hemts Using ZrO2 Gate Dielectric with Tuneable Charge

GaN-based high electron mobility transistors (HEMTs) are of significant interest for next-generation RF power amplifiers and monolithic microwave integrated circuits (MMICs). The integration of a gate dielectric in a MOS-HEMT device has been shown to offer significantly reduced gate leakage, resulting in improved reliability and reduced off-state power consumption. ZrO2 has attracted increasing attention as a candidate gate insulator for GaN-based HEMTs, due to a high dielectric constant (25), large bandgap (5.9 eV), and high breakdown voltage (15-20 MV/cm). We have previously reported high positive threshold voltage in unpassivated HEMT structures with recessed barrier layers and ZrO2 gate dielectrics deposited using zirconium (IV) tert-butoxide (ZTB) as the Zr precursor [1]. In this work, we compare these devices to structures incorporating the more common tetrakis(dimethylamino)zirconium (TDMA-Zr) precursor, which is expected to exhibit less fixed oxide charge. Combined with the optional barrier recess step, we demonstrate threshold voltage control over a range of 7V for a given HEMT layer structure. We also report the integration of SiNX passivation layers and an evaluation of the dynamic switching performance of the devices. AlGaN/GaN HEMT devices structures were grown on Si substrates by MOCVD, and devices were fabricated following standard GaN device process steps described elsewhere [1]. ZrO2 layers were deposited by atomic layer deposition using both ZTB and TDMA-Zr precursors and deionized water. Ellipsometry and X-ray photoelectron spectroscopy (XPS) were used to verify thickness and identify film stoichiometry. Capacitance-voltage measurements were initially used to characterize the oxide. A dielectric constant of 25 was extracted, and interface trap density was on the order of ~1x1012, dependent upon the nature of the oxide and the surface upon which it was deposited (HEMT structure vs GaN MOS capacitor). Gated Hall measurements were used to characterize the 2DEG mobility and sheet carrier density, both in the HEMT structure and in the recessed region under the gate. The non-recessed devices exhibit comparable current density, transconductance, and ON-resistance. The threshold voltage is shifted positive for device structures incorporating the ZTB-derived ZrO2 film, approaching enhancement mode even without the barrier recess and demonstrating an exceptionally high +4V with a barrier recess. The mechanism for this is proposed to be the presence of negative charge in the oxide film, potentially due to excess oxygen in the film. The presence of such charge was verified on GaN capacitor structures. In contrast, the TDMA-Zr-derived ZrO2 films exhibit a negative VT shift due to the thicker effective barrier, just reaching enhancement mode operation even with a full barrier recess. The breakdown voltage was comparable among all device structures both with and without recess. As expected, the gate leakage was suppressed over 5 orders of magnitude compared to the reference Schottky gated HEMT. Pulsed I-V measurements indicate a degraded current collapse behavior in the ZTB-based devices, which is expected as the negative charge from the oxide would be expected to enhance the charge trapping effect. In contrast, the TDMA-Zr-based device structures exhibit comparable current collapse to the reference device, and possibly even represent an improvement due to reduced trapping under the gate in the MOS structure. Similar behavior in the recessed gate structure indicates minimal permanent damage from the plasma recess etch. In conclusion, we have demonstrated enhancement mode AlGaN/GaN MOS-HEMTs with a thin ALD-ZrO2 gate oxide and barrier recess. The integration of this particular high-k dielectric in the device structure results in a positive threshold voltage shift due to negative charge in the oxide film and at the interface, which when integrated with a barrier recess enables a VT ~+4V while suppressing gate leakage by 4 orders of magnitude compared to a reference Schottky-gated HEMT. 1. T.J. Anderson, et. al. Appl. Phys. Express 9, 071003 (2016)

Enhancement- and depletion-mode AlGaN/GaN HEMTs on 3C-SiC(111)/Si(111) pseudosubstrates

The realization of depletion-mode planar and both enhancement- and depletion-mode tri-gate high electron mobility transistors (HEMTs) based on Al0.2Ga0.8N/AlN/GaN heterostructures grown on silicon substrates using an ultrathin 3C-SiC transition layer is presented. This substrate configuration simplifies heterostructure growth compared to SiC and thick 3C-SiC substrates. The threshold voltage of the tri-gate devices strongly depends on the AlGaN/GaN body (fin) width. A transition from depletion-mode to enhancement-mode operation occurred at 110 nm body width for tri-gate devices without Si3N4 passivation, and is expected to occur at 75 nm for devices with Si3N4 passivation. Threshold voltages of −0.25/0.35 V were achieved at fin widths of 82/100 nm with/without Si3N4 passivation, respectively, for the tri-gate HEMTs in comparison to −3.5 V for the planar HEMTs. Cutoff frequencies fT of 45 GHz and maximum frequencies of oscillation fmax of 50 GHz have been measured for our best 100-nm tri-gate enhancement-mode HEMTs, while depletion-mode planar HEMTs with the same gate length showed 110 GHz for both fT and fmax. This demonstrates the applicability of the developed substrate configuration for high-performance device applications.

Efficient III-Nitride MIS-HEMT devices with high-κ gate dielectric for high-power switching boost converter circuits

The paper reports the results of a systematic theoretical study on efficient recessed-gate, double-heterostructure, and normally-OFF metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs), HfAlOx/AlGaN on Al2O3 substrate. In device architecture, a thin AlGaN layer is used in the AlGaN graded barrier MIS-HEMTs that offers an excellent enhancement-mode device operation with threshold voltage higher than 5.3 V and drain current above 0.64 A/mm along with high on-current/off-current ratio over 107 and subthreshold slope less than 73 mV/dec. In addition, a high OFF-state breakdown voltage of 1200 V is achieved for a device with a gate-to-drain distance and field-plate length of 15 μm and 5.3 μm, respectively at a drain current of 1 mA/mm with a zero gate bias, and the substrate grounded. The numerical device simulation results show that in comparison to a conventional AlGaN/GaN MIS-HEMT of similar design, a graded barrier MIS-HEMT device exhibits a better interface property, remarkable suppression of leakage current, and a significant improvement of breakdown voltage for HfAlOx gate dielectric. Finally, the benefit of HfAlOx graded-barrier AlGaN MIS-HEMTs based switching devices is evaluated on an ultra-low-loss converter circuit.

GaN nanowire arrays with nonpolar sidewalls for vertically integrated field-effect transistors

Vertically aligned gallium nitride (GaN) nanowire (NW) arrays have attracted a lot of attention because of their potential for novel devices in the fields of optoelectronics and nanoelectronics. In this work, GaN NW arrays have been designed and fabricated by combining suitable nanomachining processes including dry and wet etching. After inductively coupled plasma dry reactive ion etching, the GaN NWs are subsequently treated in wet chemical etching using AZ400K developer (i.e., with an activation energy of 0.69 ± 0.02 eV and a Cr mask) to form hexagonal and smooth a-plane sidewalls. Etching experiments using potassium hydroxide (KOH) water solution reveal that the sidewall orientation preference depends on etchant concentration. A model concerning surface bonding configuration on crystallography facets has been proposed to understand the anisotropic wet etching mechanism. Finally, NW array-based vertical field-effect transistors with wrap-gated structure have been fabricated. A device composed of 99 NWs exhibits enhancement mode operation with a threshold voltage of 1.5 V, a superior electrostatic control, and a high current output of >10 mA, which prevail potential applications in next-generation power switches and high-temperature digital circuits.