Enhancement Mode Metal Oxide Semiconductor Research Articles

High-performance InAlGaN/GaN enhancement-mode MOS-HEMTs grown by pulsed metal organic chemical vapor deposition**Project supported by the National Postdoctoral Program for Innovative Talents, China (Grant No. BX201700184) and the National Key Research and Development Program of China (Grant Nos. 2016YFB0400105 and 2017YFB0403102).

Pulsed metal organic chemical vapor deposition was employed to grow nearly polarization matched InAlGaN/GaN heterostructures. A relatively low sheet carrier density of 1.8×1012 cm−2, together with a high electron mobility of , was obtained for the prepared heterostructures. The surface morphology of the heterostructures was also significantly improved, i.e., with a root mean square roughness of 0.29 nm in a scan area. In addition to the improved properties, the enhancement-mode metal–oxide–semiconductor high electron mobility transistors (MOS-HEMTs) processed on the heterostructures not only exhibited a high threshold voltage (VTH) of 3.1 V, but also demonstrated a significantly enhanced drain output current density of 669 mA/mm. These values probably represent the largest values obtained from the InAlGaN based enhancement-mode devices to the best of our knowledge. This study strongly indicates that the InAlGaN/GaN heterostructures grown by pulsed metal organic chemical vapor deposition could be promising for the applications of novel nitride-based electronic devices.

GaN-Based Enhancement-Mode Metal–Oxide–Semiconductor High-Electron Mobility Transistors Using LiNbO3Ferroelectric Insulator on Gate-Recessed Structure

To fabricate AlGaN/gallium nitride (GaN) enhancement-mode metal-oxide-semiconductor high-electron mobility transistors (E-MOSHEMTs), the gate-recessed structure and the LiNbO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ferroelectric film were utilized in this paper. The LiNbO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ferroelectric films deposited on the photoelectrochemically etched gate-recessed regions of the AlGaN/GaN E-MOSHEMTs as the gate insulator using a pulsed laser deposition system. The polarization-induced charges of the 2-D electron gas resided on the interface between the AlGaN and GaN layers could be modulated by the C <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> domains of the crystalline (006) LiNbO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> ferroelectric films annealed in an oxygen ambience at 600°C for 30 min. When the 15-nm-thick AlGaN was formed in the gate-recessed regions, the threshold voltage and the maximum transconductance of the resulting gate-recessed LiNbO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /AlGaN/GaN E-MOSHEMTs were +0.40 V and 56.0 mS/mm, respectively. Furthermore, the flicker noise was the dominant noise in the resulting E-MOSHEMTs. The associated normalized low-frequency noise power density of 8.1 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> Hz <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> was measured.

Flash MOS‐HFET operational stability for power converter circuits

AbstractThe enhancement mode metal oxide semiconductor heterojuntion field effect transistor with a flash gate stack (Flash MOS‐HFET) device structure is demonstrated as the switching device in a boost converter circuit operating at 1 MHz. The Flash MOS‐HFET device maintains a constant threshold voltage for the duration of circuit operation at temperatures up to 125 °C. This is the first report of Flash MOS‐HFET operation at high temperature without charge loss over time resulting in negative threshold voltage shift. The Flash MOS‐HFET structure therefore is not limited by charge loss and can be inserted into power electronic device circuits as a traditional enhancement mode device. (© 2014 WILEY‐VCH Verlag GmbH &amp; Co. KGaA, Weinheim)

Epitaxial Growth of High-κ Dielectrics for GaN MOSFETs

ABSTRACTHigh-dielectric constant (high-κ) oxide growth on hexagonal-GaN (on sapphire) is examined for potential use in enhancement-mode metal oxide semiconductor field effect transistor (MOSFET). Enhancement-mode MOSFET devices (ns &gt; 4×1013 cm−2) offer significant performance advantages, such as greater efficiency and scalability, as compared to heterojunction field effect transistor (HFET) devices for use in high power and high frequency GaN-based devices. High leakage current and current collapse at high drive conditions suggests that the use of a high-κ insulating layer is principle for enhancement-mode MOSFET development. In this work, rare earth oxides (Sc, La, etc.) are explored due to their ideal combination of permittivity and high band gap energy. However, a substantial lattice mismatch (9-21%) between the rare earth oxides and the GaN substrate results in mid-gap defect state densities and growth dislocations. The epitaxial growth of the rare earth oxides by molecular beam epitaxy (MBE) on native oxide passivated-GaN is examined in an effort to minimize these growth related defects and other growth-related limitations. Growth of the oxide on GaN is characterized analytically by RHEED, XRD, and XPS. Preliminary MOS electrical analysis of a 50 Å La2O3 on GaN shows superior leakage performance as compared to significantly thicker Si3N4 dielectric.

Low Temperature Selected Area Re-Growth of Ohmic Contacts for III-N FETs

AbstractGaN has a wide band gap energy, high electron mobility, high saturation velocity, and excellent thermal properties making it a promising material for high power and high frequency electronic devices. The development of enhancement mode GaN metal oxide semiconductor (MOS) transistors has been elusive due to the non-availability of a good insulating gate dielectric and the difficulty in forming of ohmic source/drain regions. Ion-implantation of dopants causes severe lattice damage requiring a high temperature post-implant anneal and has not been a successful method to obtain acceptable low-resistance source/drain regions. At the same time, gate dielectrics for most compound semiconductors, in addition to difficulties in minimizing the density of interface states which pin the Fermi level by inducing trap levels in the midgap, are degraded by instabilities as a result of high temperature annealing. The paper presents the development ohmic source/drain contacts for GaN MOSFETs by selected area epitaxial regrowth. Re-growth of GaN on patterned substrates by metal-organic chemical vapor deposition (MOCVD) employs a growth regime to decrease the enhanced growth rates and island formation that result from the diffusion of precursors to the selected area. The enhanced growth rate is 4.5μm/hr compared to 0.5μm/hr of the as-grown GaN on the unpatterned substrate. The enhanced growth rate also results in heavily porous GaN. Selected area growth, device processing, the material and device characterization results will be presented. In particular the selected area growth of doped contacts in the 800°C temperature range leads to superior morphology and contact resistance as compared to similar contacts grown at 1060°C. The contact resistivity of the n+ re-growth region measured was ∼2×10-4 Ω-m and the morphology of the re-grown region was comparable to the as-grown GaN with an RMS roughness ∼1.4nm. The success of fabricating low temperature contacts for GaN enhancement mode MOS transistors is a critical step in fabricating these devices opening new applications.

Circular and linear enhancement-mode 6H-SiC MOSFETs for high temperature applications

Direct current measurements are performed up to 673K at circular and linear (shown in parenthesis) enhancement-mode metal oxide semiconductor field effect transistors (MOSFETs). These devices are fabricated on a p-type 6H-SiC epitaxial layer with a doping concentration NA ≈ 1 × 1016 cm−1. The n+ source/drain regions and the p+ regions for the channel stops are achieved by ion implantation of nitrogen and aluminum, respectively. Both MOSFET geometries show excellent output characteristics with a good saturation behavior even at elevated temperatures. The inversion layer mobility μn extracted in the linear region is 38 cm2·V−1·s−1 (35 cm2·V−1·s−1) and reveals a weak dependence on temperature with a maximum of 46 cm2·V−1·s−1 (42 cm2·V−1·s−1) at about 473K. Regarding the transfer characteristics, the drain current ID can be well modulated by the gate-source voltage VGS resulting in an Ion/Loff-ratio of 108 (108) at 303K and 105 (106) at 673K. In the subthreshold regime, ID can be pinched off well below 10 pA with a subthreshold swing of 150 mV/decade (155 mV/decade) at room temperature. The threshold voltage VT as a function of temperature shows two linear sections with negative temperature coefficients of −6.8 mV·K−1 (−6.8 mV·K−1) from 303 to 423K and −2.5 mV·K−1 (−2.0 mV·K−1) from 423 to 673K. By measuring VT as a function of bulk-source voltage VBS at different temperatures, NA can be directly estimated at a transistor and gives 9.6 × 1015 cm−3 (9.8 × 1015 cm−3). The measured bulk Fermi potential Φf of the p-type epitaxial layer deviates less than 10% from the calculated value at a given temperature.

Electrical characteristics of a polyaniline/silicon hybrid field-effect transistor gas sensor

The fabrication of an array of polyaniline/silicon hybrid field-effect transistors is reported. The DC electrical characteristics have been found to be similar to those of conventional enhancement-mode metal–oxide–semiconductor devices. Investigations into the capacitance-voltage characteristics, the temperature dependence of the threshold voltage and the isothermal operating point were undertaken for devices with and without the polymeric material deposited within gaps in the gate electrodes. A delay observed in the response of the drain current on application of a gate voltage is shown to be dependent on both temperature and the presence of certain gases. This effect can be used to detect reversibly nitrogen dioxide at a concentration of 8 parts per million.

An InSb integrated photo-MOSFET fabricated by photo-enhanced chemical vapour deposition

A new output-controllable InSb infrared (i.r.) detector is proposed. The detector is fabricated by monolithically integrating an InSb p-n junction with an InSb p-channel enhancement mode metal oxide semiconductor field effect transistor (MOSFET). During operation, a photocurrent generated near the source junction is controllably switched to the drain terminal by a gate of the integrated MOSFET. The observed internal quantum efficiency in the ‘on’ state is as high as 85%. Photocurrent on-off ratios are between 260 and 730, improving with increasing channel length. For longchannel devices, the photocurrent in the ‘off’ state is limited by undesired leakage paths. The new structure can be used as an output-controllable i.r. detector.

Shallow junctions for 0.1 μm n-type metal–oxide semiconductor devices

The n+/p junctions for 0.1‐μm‐gate n‐type metal–oxide semiconductor must be no deeper than about 30 nm in order to preserve long‐channel behavior in the enhancement mode metal–oxide semiconductor field‐effect transistor. We report junctions formed by implantation of antimony or arsenic of depth 16–64 nm. They have been characterized by secondary ion mass spectroscopy, Rutherford backscattering spectroscopy lattice location studies, transmission electron microscopy, and electrical measurements.