Enhancement-mode Characteristics Research Articles

Enhancement-Mode Carbon Nanotube Optoelectronic Synaptic Transistors with Large and Controllable Threshold Voltage Modulation Window for Broadband Flexible Vision Systems.

The development of large-scale integration of optoelectronic neuromorphic devices with ultralow power consumption and broadband responses is essential for high-performance bionics vision systems. In this work, we developed a strategy to construct large-scale (40 × 30) enhancement-mode carbon nanotube optoelectronic synaptic transistors with ultralow power consumption (33.9 aJ per pulse) and broadband responses (from 365 to 620 nm) using low-work function yttrium (Y)-gate electrodes and the mixture of eco-friendly photosensitive Ag2S quantum dots (QDs) and ionic liquids (ILs)-cross-linking-poly(4-vinylphenol) (PVP) (ILs-c-PVP) as the dielectric layers. Solution-processable carbon nanotube thin-film transistors (TFTs) showed enhancement-mode characteristics with the wide and controllable threshold voltage window (-1 V∼0 V) owing to use of the low-work-function Y-gate electrodes. It is noted that carbon nanotube optoelectronic synaptic transistors exhibited high on/off ratios (>106), small hysteresis and low operating voltage (≤2 V), and enhancement mode even under the illumination of ultraviolet (UV, 365 nm), blue (450 nm), and green (550 nm) to red (620 nm) pulse lights when introducing eco-friendly Ag2S QDs in dielectric layers, demonstrating that they have the strong fault-tolerant ability for the threshold voltage drifts caused by various manufacturing scenarios. Furthermore, some important bionic functions including a high paired pulse facilitation index (PPF index, up to 290%), learning and memory function with the long duration (200 s), and rapid recovery (2 s). Pavlov's dog experiment (retention time up to 20 min) and visual memory forgetting experiments (the duration of high current for 180 s) are also demonstrated. Significantly, the optoelectronic synaptic transistors can be used to simulate the adaptive process of vision in varying light conditions, and we demonstrated the dynamic transition of light adaptation to dark adaptation based on light-induced conditional behavior. This work undoubtedly provides valuable insights for the future development of artificial vision systems.

Chemically dedoped PEDOT:PSS films with an amidine/polymer overcoating and their applications as a semiconducting channel in organic field-effect transistors and inverters

We investigate the properties of a conducting polymer composite of poly(3,4-ethylenedioxythiophene):poly(styrene sulfonate) (PEDOT:PSS) after chemical dedoping with an amidine base and demonstrate the applications of the dedoped films as a semiconducting channel in a transistor and an inverter. We observe that PEDOT:PSS can be chemically transformed from a conductor to a semiconductor through a post-treatment with 1,5-diazabicyclo[4.3.0]non-5-ene (DBN), which can donate electrons to the oxidized PEDOT chains and screen negative charges of PSS by salt formation. Both appearance of visible absorption bands and disappearance of (bi)polaronic absorption bands are observed in the DBN-treated PEDOT:PSS film, suggesting the effective dedoping. Compositional depth profiling and morphological analyses show that two distinct layers evolve after chemical dedoping and that the majority of internal PEDOT chains are dedoped over the whole film. We also introduce an overcoating layer using polyvinylpyrrolidone (PVP) with DBN to get more stable PEDOT:PSS films in a dedoped state. Organic field-effect transistors (OFETs) with the dedoped PEDOT:PSS film as a semiconducting channel show the typical p-type enhancement-mode characteristics without any doping-induced shift of threshold voltage. The pinch-off, hard saturation, and distinguishable switching characteristics with on-to-off current ratio of 104 are observed without redoping. We also demonstrate a logic circuit from the OFET as a proof-of-concept of semiconducting nature of PEDOT:PSS.

P-GaN Gated AlGaN/GaN E-mode HFET Fabricated with Selective GaN Etching Process

An O₂ based selective GaN etching process was developed herein for use in p-GaN gated AlGaN/GaN heterojunction field-effect transistor fabrication, where precise control of the p-GaN etching was an important process step that determined the device characteristics. The p-GaN layer was etched by a two-step process: low damage BCl₃/Cl₂ plasma etching in conjunction with Cl₂/N₂/O₂ based selective etching. A high selectivity of 53:1 for the p-GaN:AlGaN was achieved by the Cl₂/N₂/O₂ plasma etching. The device fabricated by the optimized etching process exhibited excellent enhancement-mode characteristics, i.e., a threshold voltage of 2.45 V, a specific on-resistance of 5.55 mΩ·cm², an on/off ratio of ~109, and an off-state breakdown voltage of >1100 V.

Robust Gate Driver on Array Based on Amorphous IGZO Thin-Film Transistor for Large Size High-Resolution Liquid Crystal Displays

Amorphous IGZO thin-film transistors (TFTs) in an etch stop layer (ESL) structure was processed on 2500 mm $\times $ 2200 mm size substrate. The fabricated devices exhibit enhancement mode characteristics, and excellent uniformity over large area. The presented good operational stabilities under both positive gate bias temperature stress (PBTS) and negative gate bias temperature stress (NBTS) tests can well meet the requirements for pixel switching. However, considering even threshold voltage shift under long term positive bias stress might affect proper operation of the gate driver on array (GOA), a design with a pulse gating scheme is proposed, consisting of 13 TFTs and 1 capacitor, to avoid long term continuous bias stressing of the TFT. With the proposed GOA design, a 32-inch QUHD ( $7680\times 4320$ ) high-resolution liquid crystal display (LCD) panel with a 7 mm wide bezel is achieved. The reliability of the GOA circuit is well proved through standard aging tests.

Deposition of TiO2/Al2O3 bilayer on hydrogenated diamond for electronic devices: Capacitors, field-effect transistors, and logic inverters

The wide bandgap semiconductor diamond has been studied to develop high-power and high-frequency electronic devices. Here, high dielectric constant (high-k) TiO2/Al2O3 bilayers are deposited on hydrogenated diamond (H-diamond) channel layers using sputter deposition (SD) and atomic layer deposition (ALD) techniques. Thin ALD-Al2O3 films are employed as buffer layers for the SD-TiO2 and ALD-TiO2 on H-diamond to suppress plasma discharge effect and to decrease leakage current density (J), respectively. The electrical properties of the resulting TiO2/Al2O3/H-diamond metal-oxide-semiconductor (MOS) capacitors, MOS field-effect transistors (MOSFETs), and MOSFET logic inverters are investigated. With the same thickness (4.0 nm) for ALD-Al2O3 buffer layer, the ALD-TiO2/ALD-Al2O3/H-diamond MOS capacitor shows a lower J and better capacitance-voltage characteristics than the SD-TiO2/ALD-Al2O3/H-diamond capacitor. The maximum capacitance of the ALD-TiO2/ALD-Al2O3/H-diamond capacitor and the k value of the ALD-TiO2/ALD-Al2O3 bilayer are 0.83 μF cm−2 and 27.2, respectively. Valence band offset between ALD-TiO2 and H-diamond is calculated to be 2.3 ± 0.2 eV based on the element binding energies measured using an X-ray photoelectron spectroscopy technique. Both the SD-TiO2/ALD-Al2O3/H-diamond and ALD-TiO2/ALD-Al2O3/H-diamond MOSFETs show p-type, pinch-off, and enhancement mode characteristics with on/off current ratios around 109. The subthreshold swings of them are 115 and as low as 79 mV dec−1, respectively. The ALD-TiO2/ALD-Al2O3/H-diamond MOSFET logic inverters, when coupled with load resistors, show distinct inversion characteristics with gains of 6.2–12.7.

Threshold-voltage control and enhancement-mode characteristics in multilayer tin disulfide field-effect transistors by gate-oxide passivation with an alkylphosphonic acid self-assembled monolayer

We have synthesized crystals of two-dimensional layered tin disulfide (SnS2) by chemical vapor transport and fabricated field-effect transistors based on mechanically exfoliated SnS2 multilayer platelets. We demonstrate that the threshold voltage of these transistors can be modified by passivating the gate-oxide surface with a self-assembled monolayer of an alkylphosphonic acid, affording transistors with desirable enhancement-mode characteristics. In addition to a positive threshold voltage and a large on/off current ratio, these transistors also have a steep subthreshold swing of 4 V/decade.

Effect of Ti∕Cu Source∕Drain on an Amorphous IGZO TFT Employing SiNx Passivation for Low Data-Line Resistance

We successfully fabricated a-IGZO TFTs with a Ti/Cu source/drain (S/D) in order to reduce the data-line resistance. SiNx passivation was used to protect the Cu from Cu-oxygen diffusion. The TFTs exhibited normal enhancement-mode characteristics compared to the TFT employing a Mo S/D, which behaved like a conductor. Our experiments suggest that the Ti/Cu S/Ds control the channel resistivity of the fabricated TFT lower than the Mo case. We found an indium-deficient IGZO layer under the Ti contact; this is thought to be the origin which reduces oxygen vacancy concentration in the channel. © 2012 The Electrochemical Society. [DOI: 10.1149/2.003205esl] All rights reserved.

Effect of MgO buffer layer thickness on the electrical properties of MgZnO thin film transistors fabricated by plasma assisted molecular beam epitaxy

We report the fabrication and electrical characteristics of thin film transistors based on MgZnO thin films with different thicknesses of MgO buffer layer. The MgZnO thin films with MgO buffer layers were grown on SiO 2/p-Si substrates by plasma assisted molecular beam epitaxy. The effects of the buffer layer thickness on the structural properties of MgZnO films are investigated by X-ray diffraction, and the results show that the crystal quality of the MgZnO film is enhanced with 4 nm MgO buffer layer. The MgZnO TFT with 4 nm MgO buffer layer exhibits an n-type enhancement mode characteristics with a field effect mobility of 1.85 cm 2/V s, a threshold voltage of 27.6 V and an on/off ratio of above 10 6.

ZnO Field-Effect Transistor Fabricated by RF Magnetron Suputtering and Lithographic/Wet Etching Processes

The fabrication of zinc oxide （ZnO）based thin-film field-effect transistors (TFTs) on p-Si substrates by rf magnetron sputtering, photolithography and wet etching processes was presented. Bottom-gate-type thin film transistors using ZnO as an active channel layer were constructed, and their properties were characterized by atomic force microscope, X-ray diffraction and I-V measurements. The fabricated ZnO transistors exhibited enhancement mode characteristics with the on-to-off current ratio of ∼105 and the threshold voltage of 10V. It is believed that the ZnO TFTs fabricatd by the simple and low-cost technique could be applicable to electronic devices.

Thin film transistors based on TiO 2 fabricated by using radio-frequency magnetron sputtering

This study demonstrates that nanocrystalline TiO 2 thin films were deposited on ITO/glass substrate by radio-frequency magnetron sputtering. Field-emission scanning electron microscope (FE-SEM) and atomic force microscopic (AFM) images showed the morphology of TiO 2 channel layer with grain size and root-mean-square (RMS) roughness of 15 and 5.39 nm, respectively. TiO 2 thin-film transistors (TFTs) with sputter-SiO 2 gate dielectric layer were also fabricated. It was found that the devices exhibited enhancement mode characteristics with the threshold voltage of 7.5 V. With 8-μm gate length, it was also found that the I on /off ratio and off-state current were around 1.45×10 2 and 10 nA, respectively.

Enhancement‐Mode Silicon Nanowire Field‐Effect Transistors on Plastic Substrates

Top-gate field-effect transistors (FETs) with n-channels consisting of n+–p–n+ doped Si nanowires are constructed on plastic substrates via the conventional top-down approach. These top-gate FETs show excellent enhancement-mode characteristics (see image).

Effects of the channel thickness on the structural and electrical characteristics of room-temperature fabricated ZnO thin-film transistors

We report the fabrication and characteristics of ZnO thin-film transistors (TFTs) having different channel thicknesses. The ZnO films were deposited as active channel layers on SiO2/p-Si substrates by rf magnetron sputtering at room temperature. Effects of the channel thickness on the structural and electrical properties of ZnO TFTs using a bottom-gate configuration were investigated. The crystalline quality and channel conductance of the ZnO films were enhanced as the channel thickness increased. The ZnO TFT with the optimized channel thickness exhibited enhancement mode characteristics with the threshold voltage of 9.9 V, the on-to-off current ratio of ∼105 and the field-effect mobility of 0.1 cm2 V−1 s−1. This research implies that ZnO TFTs produced by a simple and low-cost technique could be applicable to electronic devices.

The effects of surface treatment on device performance in pentacene-based thin film transistor

We report on the influence of surface treatment using hexamethyldisilazane (HMDS) on device performance of pentacene-based thin film transistor. The samples with surface treatment using HMDS show higher mobility, lower subthreshold slope, and lower off-current compared to the untreated samples. We have also investigated the effect of various coating methods of HMDS on device performance. In the case of post-baked samples after spin coating, the improvements of mobility and on-current are larger than those of spin-coated samples. Especially a dip-coated sample has threshold voltage of −4.11 V and turn-on voltage of −0.03 V, showing the enhancement mode characteristics, which is useful for the operation as a circuit and a switch device for active-matrix displays. However, the mobility of dip-coated sample is one order lower than that of spin-coated sample, and hysteresis is larger than that of spin-coated sample.

Silicon nanowires as enhancement-mode Schottky barrier field-effect transistors

Silicon nanowire field-effect transistors (SiNWFETs) have been fabricated with ahighly simplified integration scheme to function as Schottky barrier transistorswith excellent enhancement-mode characteristics and a high on/off current ratio∼107. SiNWFETs show significant improvement in the thermal emission leakage(∼6 × 10−13 A µm−1) compared to reference FETs with a larger channel width(∼7 × 10−10 A µm−1). The drain current level depends substantially on the contact metal work functionas determined by examining devices with different source/drain contacts of Ti(≈4.33 eV)and Cr (≈4.50 eV). The different conduction mechanisms for accumulation- and inversion-mode operationare discussed and compared with two-dimensional numerical simulation results.

Moisture sensitive field effect transistors using gate structure

A humidity sensing device, named a moisture sensitive field effect transistor (HUMIFET) has been fabricated on an n-type Si wafer using conventional VLSI technology. A series of sensors, each having area have been designed on a single Si wafer. The FET device is an n-channel MISFET with a duplex gate structure. A humidity sensitive layer of an anodically oxidized film of Al covers the under-gate electrode area and serves as a humidity sensitive film. The structure of the HUMIFET is and a thin porous gold (Au) layer on acts as the upper gate electrode. The device shows an enhancement mode characteristics with a threshold voltage of V at 33% relative humidity (RH) level which increases with decreasing RH level. The capacitance of the sensing film is measured and its temperature dependence is also observed. The drain current of the device is measured with RH at constant gate and drain voltages and the hysteresis area is found. The sensitivity of the device is 4.8 for the whole range of RH levels at constant gate and drain voltages. During a one month study on reproducibility, the device is found to be very stable. The response and recovery times of the device are and s respectively.

Humidity sensitive field effect transistors

A new device, named humidity sensitive field effect transistors (HUSFETs), for integrated humidity sensors has been fabricated using conventional silicon microtechnology. The insulator structure of this HUSFETs is TiO 2/Si 3N 4SiO 2 and the water molecular permeable electrode is thin porous gold. The fabricated devices showed typical enhancement mode characteristics and the threshold voltage was about 2.7 V in 60% RH. It can be seen that the threshold voltages of HUSFET decreased from 3.0 to 2.4 V and the drain current increased from 208 to 464 μA according to increasing relative humidities from 30 to 90%. The sensitivity of HUSFET is 3.2 μA/RH, when the drain and gate voltages are constant.

High-performance poly-Si TFTs with ECR-plasma hydrogen passivation

High-performance thin-film transistors (TFTs) with electron-cyclotron resonance (ECR) plasma hydrogen passivation fabricated by the use of laser-recrystallized multiple-strip-structure poly-Si film are discussed. These TFTs have n-channel enhancement-mode characteristics with a large transconductance, a high switching ratio, and a threshold voltage as low as 0.4 v. The ECR-plasma hydrogen passivation of laser-recrystallized poly-Si, reduces the trap density of poly-Si and increases the carrier mobility thus, desirable TFT characteristics are obtained. This passivation increased the transconductance (g/sub m/) of a TFT and decreased the leakage current between the source and the drain. As a result, a switching ratio as high as 2.5*10/sup 9/ and very low leakage current of the order of 10/sup 14/ A can be achieved by these high-performance TFTs. >

Large on/off current ratio and low leakage current poly-Si TFTs with multichannel structure

High-performance thin-film transistors (TFTs) have been fabricated on a quartz substrate by the use of a laser-annealed multiple-strip-structure poly-Si film as a semiconductor. By recrystallization of a multiple-strip-structure poly-Si with CW-Ar laser, the carrier trap density of poly-Si can be reduced to obtain the preferential characteristics of a TFT. So, these poly-Si TFTs have n-channel enhancement-mode characteristics with threshold voltage as low as 0.4 V and large transconductance. Furthermore, a very large ON/OFF current ratio is obtained as eight orders of magnitude and the leakage current between the source and the drain is revealed to be as low as approximately 10/sup -13/ A. >

High-voltage poly-Si TFTs with multichannel structure

High-voltage (>100-V) and large-transconductance poly-Si thin-film transistors (TFTs) have been fabricated on quartz substrates by the use of laser-recrystallized multiple-strip poly-Si films as semiconductors in the channel regions. The TFTs have an offset gate structure between the source and the gate (L/sub OFF,1/), and between the gate and the drain (L/sub OFF,2/). With the nonsymmetric offset gate structure at L/sub OFF,1/=3 mu m and L/sub OFF,2/=15 mu m, the TFTs have a large transconductance of 520 mu S and exhibit low-threshold n-channel enhancement-mode characteristics. Simultaneously, a very large ON/OFF current ratio (above 10/sup 7/) and a low leakage current of 2*10/sup -10/ A occur at the high drain voltage of V/sub D/=100 V. The breakdown voltage V/sub BD/ of the TFT depends strongly on L/sub OFF,2/, so V/sub BD/ can increase with increasing L/sub OFF,2/ to 110 V at L/sub OFF,2/=10 mu m, 130 V at L/sub OFF,2/=15 mu m, and 170 V at L/sub OFF,2/=20 mu m.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Fully isolated lateral bipolar—MOS transistors fabricated in zone-melting-recrystallized Si films on SiO2

A four-terminal device that can be operated either as a lateral n-p-n bipolar transistor or as a conventional n-channel MOSFET has been fabricated in silicon-on-insulator films prepared by graphite-strip-heater zone-melting recrystallization. Common-emitter current gain close to 20 and emitter-base breakdown voltage in excess of 10 V have been obtained for bipolar operation. As a MOSFET, the device exhibits well-behaved enhancement-mode characteristics with a field-effect mobility of ∼ 600 cm2/V.s and drain breakdown voltage exceeding 15 V.