Transconductance Enhancement Research Articles

Cryogenic operation of a 24 GHz MMIC SiGe HBT medium power amplifier

The performance of a SiGe heterojunction bipolar transistor (HBT) millimetre-wave power amplifier (PA) operating at cryogenic temperature was reported and analysed for the first time. A 24 GHz two-stage medium PA employing common-emitter and common-base SiGe power HBTs in the first and the second stage, respectively, showed a significant power gain increase at 77 K in comparison with that measured at room temperature. Detailed analyses indicate that cryogenic operation of SiGe HBT-based PAs mainly affects (improves) the performance of the SiGe HBTs in the circuits due to transconductance enhancement through magnified, favourable changes of SiGe bandgap due to cooling (ΔEg/kT) and minimized thermal effects, with little influence on the passive components of the circuits.

The Effect of Thick Interconnections Formed by Gold Electroplating on the Characteristics of Metal–Oxide–Semiconductor Field-Effect Transistors

This paper describes the electrical properties of metal–oxide–semiconductor field-effect transistors (MOSFETs) with thick gold (Au) interconnections formed by electroplating. The tensile stress loaded in the channel region of MOSFETs with thick Au interconnections induces a slight (2–5%) enhancement of transconductance, gm, in N-channel (N-ch) MOSFETs. Hot-carrier stress tests with and without thick Au interconnections were carried out to investigate the long-term reliability of N-ch MOSFETs. The lifetime of gm with thick Au interconnections was estimated to be over ten years, which is the same as that without them. These results demonstrate that thick Au interconnections do not deteriorate the electrical properties or long-term reliability of underlying MOSFETs.

Transconductance enhancement method for operational transconductance amplifiers

An improved recycling structure for an operational transconductance amplifier is proposed. The proposed structure separates the AC path from the DC path, and achieves a significant boost in transconductance under the same power and area budget. A folded-cascode amplifier employing the improved recycling structure was implemented in SMIC standard 0.13 μm CMOS process. Simulation results show that the enhancement of transconductance leads to 230% improvement in gain-bandwidth product and 13 dB boost in gain compared with the conventional folded cascode.

Performance Enhancements in Scaled Strained-SiGe pMOSFETs With $ \hbox{HfSiO}_{x}/\hbox{TiSiN}$ Gate Stacks

The short-channel performance of compressively strained Si0.77Ge0.23 pMOSFETs with HfSiOx/TiSiN gate stacks has been characterized alongside that of unstrained-Si pMOSFETs. Strained-SiGe devices exhibit 80% mobility enhancement compared with Si control devices at an effective vertical field of 1 MV middotcm-1. For the first time, the on-state drain-current enhancement of intrinsic strained-SiGe devices is shown to be approximately constant with scaling. Intrinsic strained-SiGe devices with 100-nm gate lengths exhibit 75% enhancement in maximum transconductance compared with Si control devices, using only ~20% Ge (~0.8% strain). The origin of the loss in performance enhancement commonly observed in strained-SiGe devices at short gate lengths is examined and found to be dominated by reduced boron diffusivity and increased parasitic series resistance in compressively strained SiGe devices compared with silicon control devices. The effective channel length was extracted from I- V measurements and was found to be 40% smaller in 100-nm silicon control devices than in SiGe devices having the same lithographic gate lengths, which is in good agreement with the metallurgical channel length predicted by TCAD process simulations. Self-heating due to the low thermal conductivity of SiGe is shown to have a negligible effect on the scaled-device performance. These findings demonstrate that the significant on-state performance gains of strained-SiGe pMOSFETs compared with bulk Si devices observed at long channel lengths are also obtainable in scaled devices if dopant diffusion, silicidation, and contact modules can be optimized for SiGe.

Demonstration of Transconductance Enhancement on (110) and (001) Strained-Nanowire FETs

Enhancement of transconductance for strained nanowire transistors (s-nwFETs) on (001) and (110) planes are demonstrated by evaluating Ids-Vbg curves of the devices. Normalized transconductance, gm*, for <100> direction s-nwFETs is enhanced by a factor of 2.16 for n-type on (001) plane and 1.83 for p-type on (110) plane. This is due to the lighter effective mass of electrons/holes along the selected channel direction.

A Stepped Oxide Hetero-Material Gate Trench Power MOSFET for Improved Performance

In this brief, we propose a new stepped oxide hetero-material trench power MOSFET with three sections in the trench gate (an N <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> poly gate sandwiched between two P <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> poly gates) and having different gate oxide thicknesses (increasing from source side to drain side). The different gate oxide thickness serves the purpose of simultaneously achieving the following: 1) a good gate control on the channel charge and 2) a lesser gate-to-drain capacitance. As a result, we obtain higher transconductance as well as reduced switching delays, making the proposed device suitable for both RF amplification and high-speed switching applications. In addition, the sandwiched gate with different work-function gate materials modifies the electric field profile in the channel, resulting in an improved breakdown voltage. By using 2-D simulations, we have shown that the proposed device structure exhibits about 32% enhancement in breakdown voltage, 25% reduction in switching delays, 20% enhancement in peak transconductance, and 10% reduction in figure of merit (product of ON-resistance and gate charge) as compared to the conventional trench-gate MOSFET.

Gate-All-Around n-MOSFETs With Uniaxial Tensile Strain-Induced Performance Enhancement Scalable to Sub-10-nm Nanowire Diameter

The effects of high-level uniaxial tensile strain on the performance of gate-all-around (GAA) Si n-MOSFETs are investigated for nanowire (NW) diameters down to 8 nm. Suspended strained-Si NWs with ~2-GPa uniaxial tension were realized by nanopatterning-induced unilateral relaxation of ultrathin-body 30% strained-Si-directly-on-insulator substrates. Based on these NWs, GAA strained-Si n-MOSFETs were fabricated with a Si thickness of ~8 nm and NW widths in the range of 50 nm down to 8 nm. The GAA strained-Si MOSFETs show excellent subthreshold swing and cutoff behavior, and approximately two times current drive and intrinsic transconductance enhancement compared to similar unstrained Si devices.

Transconductance Enhancement by Utilizing Pattern Dependent Oxidation in Silicon Nanowire Field-Effect Transistors

Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependant oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation reveal predominantly horizontal tensile stress in the nwFET channels. The Raman lines in the strain controlled devices display an increase in the full width half maximum, and a shift to lower wavenumber confirming that gm enhancement is due to tensile stress introduced by the PADOX approach.

Fabrication and Characterization of Suspended Uniaxial Tensile Strained-Si Nanowires for Gate-All-Around Nanowire n-MOSFETs

Suspended strained-Si nano-wires (NWs) were fabricated from a highly biaxially strained-Si substrate (with an initial stress of 2.16 GPa). Using e-beam lithography, ~25nm thick NWs with the widths in the range of 20 to 80 nm were fabricated and the stress was investigated by UV micro-Raman spectroscopy. Suspended NWs are strained to an average uniaxial tensile stress level of ~2.1 GPa which is almost independent of NW width, in the range studied in this work. Ultra-dense (25 NWs per micron) sub-20 nm suspended strained-Si NWs were fabricated using resolution-enhanced lithography to improve the Raman signal-to-noise ratio. A tensile in-plane stress level of 1.7GPa was measured for 18 nm-wide NWs at 40 nm pitch. Gate-all-around n-MOSFETs were fabricated based on these strained-Si NWs. Electrical measurements on these MOSFETs demonstrate near ideal subthreshold behavior, very high on-to-off ratio and current drive and transconductance enhancement of ~2X over unstrained NWs.

Ge wire MOSFETs fabricated by three-dimensional Ge condensation technique

We propose a novel method to form Ge nano-wire structures by utilizing a three-dimensional (3D) Ge condensation technique. Since this method needs only top-down and Si compatible processes, Ge nano-wire MOSFETs fabricated by this technique are suitable for actual LSI applications. Based on this concept, we have fabricated SiGe on insulator wire pMOSFETs with Ge content up to 92% and diameter down to 35 nm. 3× enhancement of transconductance against a control Si device has been demonstrated in pMOSFETs with Ge content of 79%, though the performance enhancement in the highest Ge content device has not been obtained yet because of the non-optimized 3D Ge condensation processes. Further performance enhancement is expected after optimizing 3D Ge condensation processes especially for higher Ge content SiGe channels.

High‐performance pMOSFETs with high Ge fraction strained SiGe‐heterostructure channel and ultrashallow source/drain formed by selective B‐doped SiGe CVD

AbstractThe improvement of current drivability and short‐channel effect is very important for ultrasmall MOS device technology. SiGe‐channel pMOSFETs are one of the most promising devices because hole mobility in the SiGe layers is enhanced. In the previous work, it has been reported that Super Self‐aligned Shallow junction Electrode (S3E) MOSFETs formed by selective B‐doped SiGe CVD are effective for the suppression of short‐channel effect. In this paper, it is clarified that the (S3E) pMOSFETs with Si0.65Ge0.35 channel are realized not only with suppression of punch‐through due to the ultrashallow B‐diffused source/drain but also with enhancement of maximum linear transconductance due to the low parasitic resistance, compared to that with the Si channel fabricated by the same process conditions. © 2008 Wiley Periodicals, Inc. Electr Eng Jpn, 165(3): 46–50, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/eej.20597

Transport properties of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors with Al2O3 of different thickness

The Al2O3 as a gate oxide and passivation was used to study the transport properties of AlGaN/GaN metal–oxide–semiconductor heterostructure field-effect transistors (MOSHFETs). Performance of the devices with Al2O3 of different thickness between 4 and 14nm prepared by metal–organic chemical vapor deposition (MOCVD) and with 4nm thick Al2O3 prepared by Al sputtering and oxidation was investigated. All MOS-devices yielded higher transconductance than their HFET counterparts, i.e. the transconductance/capacitance expected proportionality assuming the same carrier velocity was not fulfilled. A different electric field near/below the gate contact due to a reduction of traps is responsible for the carrier velocity enhancement in the channel of the MOSHFET. The trap reduction depends on the oxide used, as follows from the capacitance vs frequency dispersion for devices investigated. It is qualitatively in a good agreement with the different velocity enhancement evaluated, and devices with thinner oxide show higher traps reduction as well as higher transconductance enhancement. It is also shown that obtained conclusions can be applied well on performance of SiO2/AlGaN/GaN MOSHFETs.

Strain-induced transconductance enhancement by pattern dependent oxidation in silicon nanowire field-effect transistors

Transconductance (gm) enhancement in n-type and p-type nanowire field-effect-transistors (nwFETs) is demonstrated by introducing controlled tensile strain into channel regions by pattern dependent oxidation (PADOX). Values of gm are enhanced relative to control devices by a factor of 1.5 in p-nwFETs and 3.0 in n-nwFETs. Strain distributions calculated by a three-dimensional molecular dynamics simulation reveal predominantly horizontal tensile stress in the nwFET channels. The Raman lines in the strain controlled devices display an increase in the full width at half maximum and a shift to lower wavenumber, confirming that gm enhancement is due to tensile stress introduced by the PADOX approach.

Strain and Materials Engineering for the I-MOS Transistor With an Elevated Impact-Ionization Region

An impact-ionization MOS (I-MOS) transistor with an elevated impact-ionization region (I-region) or the L-shaped I-MOS (LI-MOS) transistor has been proposed as a promising candidate among various I-MOS structures for enhanced performance through strain and materials engineering. The elevated I-region allows for the incorporation of novel materials to induce strain and reduction in the bandgap to increase the impact- ionization activity. In addition, the LI-MOS structure is more compact and compatible with conventional CMOS processes. In this paper, we discuss and explore the relationship and impact of strain and bandgap on the generation of impact-ionization carriers. Si n-channel I-MOS transistors with Si raised source/drain (RSD), Si1-yCy RSD, and Si1-xGex RSD were studied and explored through simulations and experiments. An excellent subthreshold swing of sub-5 mV/dec at room temperature is demonstrated for the three I-MOS transistor structures. Compared to an unstrained I-MOS with Si RSD, strain-engineered I-MOS with Si0.99C0.01 RSD exhibits a twofold enhancement in both ON-state current and maximum transconductance at a gate length of 60 nm. For materials- or bandgap-engineered I-MOS with Sio.75Ge0.25 RSD, a greater enhancement of approximately three times is observed. In addition, a lower breakdown voltage and enhanced breakdown characteristics are achieved with both strain- and materials-engineered I-MOS transistors.

Transconductance enhancement of nanowire field-effect transistors by built-up stress induced during thermal oxidation

The authors report the enhancement of transconductance in nanowire field effect transistors due to build-up tensile stress during thermal oxidation. To evaluate the effect of stress, nanowires were thermally oxidized at (A) 900°C∕15min, (B) 850°C∕1h, and (C) 850°C∕1h with a subsequent 1000°C annealing. The transconductance of sample B is enhanced 2.6 times compared to sample A. No enhancement of transconductance is observed in sample C. The Raman spectra indicate tensile stress in sample B and compressive stress in sample C. This establishes that gm enhancement is due to the build-up tensile stress in nanowires, but is diminished by viscoelastic relaxation.

Low frequency noise in Si and Si/SiGe/Si PMOSFETs

Measurements of 1/f noise in Si and Si0.64Ge0.36 PMOSFETs have been compared with theoretical models of carrier tunnelling into the oxide. Reduced noise is observed in the heterostructure device as compared to the Si control. We suggest that this is primarily associated with an energy dependent density of oxide trap states and a displacement of the Fermi level at the SiO2 interface in the heterostructure relative to Si. The present study also emphasizes the important role of transconductance enhancement in the dynamic threshold mode in lowering the input referred voltage noise.

STUDY OF DUAL-MATERIAL GATE (DMG) FinFET USING THREE-DIMENSIONAL NUMERICAL SIMULATION

In this work, the novel characteristics of a FinFET with dual-material gate (DMG) are explored theoretically using a 3D numerical simulator and compared with those of a single material gate (SMG) FinFET in terms of threshold voltage roll off, drain induced barrier lowering (DIBL) and the ratio of transconductance (gm) to drain conductance (gd). Our studies show that the DMG structure achieves simultaneous suppression of short channel effects (SCEs), enhancement in carrier transport efficiency and transconductance. Also, these features can be controlled by engineering the work function and length of gate material.

Application of Microwave Plasma Gate Oxidation to Strained-Si/SiGe-on-Insulator

We have applied microwave-plasma oxidation at 400 °C to the gate oxide formation of a strained-Si/SiGe-on-insulator (SGOI) metal–oxide–semiconductor field-effect transistor (MOSFET). Application of low-temperature wet-O2 treatment to plasma oxide on strained-Si/Si0.85Ge0.15 significantly reduces the density of interface states and provides a 72% enhancement in transconductance compared with Si control devices. In the case of a thermally oxidized device, the junction leakage current was increased due to Ge condensation up to 50% Ge at the mesa island edge. On the other hand, the plasma oxide device showed a leakage current two orders of magnitude lower than that of the thermally oxidized device, owing to the suppression of the Ge condensation.

High Performance pMOSFETs with High Ge Fraction Strained SiGe-heterostructure-channel and Ultrashallow Source/Drain Formed by Selective B-Doped SiGe CVD

The improvement of current drivability and short channel effect is very important for ultrasmall MOS devices technology. SiGe-channel pMOSFETs are one of the most promising devices because hole mobility in the SiGe layers is enhanced. In the previous work, it has been reported that Super self-aligned shallow junction electrode (S3E) MOSFETs formed by selective B-doped SiGe CVD are effective for the suppression of short channel effect. In this paper, it is clarified that the (S3E) pMOSFETs with Si0.65Ge0.35-channel are realized not only with suppression of punch through due to the ultrashallow B-diffused source/drain but also with enhancement of maximum linear transconductance due to the low parasitic resistance, compared to that with the Si-channel fabricated by the same process conditions.

Improving channel carrier mobility and immunity to charge trapping of high-K NMOSFET by using stacked Y/sub 2/O/sub 3//HfO/sub 2/ gate dielectric

A stacked Y/sub 2/O/sub 3//HfO/sub 2/ multimetal gate dielectric with improved electron mobility and charge trapping characteristics is reported. Laminated hafnium and yttrium were sputtered on silicon followed by post-deposition anneal (PDA) in N/sub 2/ ambient. The new dielectric shows a similar scalability to HfO/sub 2/ reference. Analysis on flatband voltage shift indicates positive fixed charge induced by Y/sub 2/O/sub 3/. Excellent transistor characteristics have been demonstrated. Stacked Y/sub 2/O/sub 3//HfO/sub 2/, compared to HfO/sub 2/ reference with similar equivalent oxide thickness (EOT), shows 49% enhancement in transconductance and 65% increase in the peak electron mobility. These improvements may be attributed to better charge trapping characteristics of the multimetal dielectric.