Energy Overhead Research Articles

RANCE: A Randomly Centralized and On-Demand Clustering Protocol for Mobile Ad Hoc Networks

LEACH-like clustering protocols focus mainly on the low-power, low-rate, and low-wakeup network applications, and work in a multiround clustering strategy that causes frequent handovers of cluster heads (CHs), thus less support for real-time services that require stable cluster topologies. Besides, these protocols are faced with respective drawbacks, such as suboptimality of selected heads, costly node-base station (BS) energy overheads, lack of runtime cluster maintenance, etc. This article proposes RANCE, a randomly centralized and on-demand clustering protocol, aiming at prolonging nodes’ clustered time to support internodes collaboration while being energy efficient in mobile ad hoc networks. First, RANCE designs a randomly centralized CH selection mechanism in which every node in the local wireless network is eligible to initiate the centralized CH selection, so that the self-organizing characteristics of mobile ad hoc nodes can be utilized for head selection optimization. Second, taking into account the wireless volatility caused by changes of topology, obstacles, signal strength, etc., the fine-grained cluster relationships maintenance is provided by means of multilevel aliveness and adaptive bidirectional heartbeat packets. Third, RANCE works in an event-driven and on-demand manner instead of a time-triggered manner in LEACH-like protocols, to reduce the impact on continuous services caused by frequent CH handovers among all nodes. Simulation results show that RANCE provides longer clustered time (over 99% of nodes’ lifetime in networks more than 100 nodes) and good clustering scalability with high consistency at minimum energy cost, and exhibits good potentials in mobile wireless environments that are infrastructureless/poor for continuous missions.

Leveraging the Properties of mmWave Signals for 3D Finger Motion Tracking for Interactive IoT Applications

mmWave signals form a critical component of 5G and next-generation wireless networks, which are also being increasingly considered for sensing the environment around us to enable ubiquitous IoT applications. In this context, this paper leverages the properties of mmWave signals for tracking 3D finger motion for interactive IoT applications. While conventional vision-based solutions break down under poor lighting, occlusions, and also suffer from privacy concerns, mmWave signals work under typical occlusions and non-line-of-sight conditions, while being privacy-preserving. In contrast to prior works on mmWave sensing that focus on predefined gesture classification, this work performs continuous 3D finger motion tracking. Towards this end, we first observe via simulations and experiments that the small size of fingers coupled with specular reflections do not yield stable mmWave reflections. However, we make an interesting observation that focusing on the forearm instead of the fingers can provide stable reflections for 3D finger motion tracking. Muscles that activate the fingers extend through the forearm, whose motion manifests as vibrations on the forearm. By analyzing the variation in phases of reflected mmWave signals from the forearm, this paper designs mm4Arm, a system that tracks 3D finger motion. Nontrivial challenges arise due to the high dimensional search space, complex vibration patterns, diversity across users, hardware noise, etc. mm4Arm exploits anatomical constraints in finger motions and fuses them with machine learning architectures based on encoder-decoder and ResNets in enabling accurate tracking. A systematic performance evaluation with 10 users demonstrates a median error of 5.73° (location error of 4.07 mm) with robustness to multipath and natural variation in hand position/orientation. The accuracy is also consistent under non-line-of-sight conditions and clothing that might occlude the forearm. mm4Arm runs on smartphones with a latency of 19 ms and low energy overhead.

LNS-Madam: Low-Precision Training in Logarithmic Number System Using Multiplicative Weight Update

Representing deep neural networks (DNNs) in low-precision is a promising approach to enable efficient acceleration and memory reduction. Previous methods that train DNNs in low-precision typically keep a copy of weights in high-precision during the weight updates. Directly training with low-precision weights leads to accuracy degradation due to complex interactions between the low-precision number systems and the learning algorithms. To address this issue, we develop a co-designed low-precision training framework, termed LNS-Madam, in which we jointly design a logarithmic number system (LNS) and a multiplicative weight update algorithm (Madam). We prove that LNS-Madam results in low quantization error during weight updates, leading to stable performance even if the precision is limited. We further propose a hardware design of LNS-Madam that resolves practical challenges in implementing an efficient datapath for LNS computations. Our implementation effectively reduces energy overhead incurred by LNS-to-integer conversion and partial sum accumulation. Experimental results show that LNS-Madam achieves comparable accuracy to full-precision counterparts with only 8 bits on popular computer vision and natural language tasks. Compared to FP32 and FP8, LNS-Madam reduces the energy consumption by over 90% and 55%, respectively.

Reinforcement Learning-Based Joint Reliability and Performance Optimization for Hybrid-Cache Computing Servers

Computing servers play a key role in the development and process of emerging compute-intensive applications in recent years. However, they need to operate efficiently from an energy perspective viewpoint, while maximizing the performance and lifetime of the hottest server components (i.e., cores and cache). Previous methods focused on either improving energy efficiency by adopting new hybrid-cache architectures including the resistive random-access memory (RRAM) and static random-access memory (SRAM) at the hardware level, or exploring tradeoffs between lifetime limitation and performance of multicore processors under stable workloads conditions. Therefore, no work has so far proposed a co-optimization method with hybrid-cache-based server architectures for real-life dynamic scenarios taking into account scalability, performance, lifetime reliability, and energy efficiency at the same time. In this article, we first formulate a reliability model for the hybrid-cache architecture to enable precise lifetime reliability management and energy efficiency optimization. We also include the performance and energy overheads of cache switching, and optimize the benefits of hybrid-cache usage for better energy efficiency and performance. Then, we propose a runtime <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$q$ </tex-math></inline-formula> -learning-based reliability management and performance optimization approach for multicore microprocessors with the hybrid-cache architecture, jointly incorporated with a dynamic preemptive priority queue management method to improve the overall tasks’ performance by targeting to respect their end time limits. Experimental results show that our proposed method achieves up to 44% average performance (i.e., tasks execution time) improvement, while maintaining the whole system design lifetime longer than five years, when compared to the latest state-of-the-art energy efficiency optimization and reliability management methods for computing servers.

Design-Technology Co-Optimization for NVM-Based Neuromorphic Processing Elements

An emerging use case of machine learning (ML) is to train a model on a high-performance system and deploy the trained model on energy-constrained embedded systems. Neuromorphic hardware platforms, which operate on principles of the biological brain, can significantly lower the energy overhead of an ML inference task, making these platforms an attractive solution for embedded ML systems. We present a design-technology tradeoff analysis to implement such inference tasks on the processing elements (PEs) of a non-volatile memory (NVM)-based neuromorphic hardware. Through detailed circuit-level simulations at scaled process technology nodes, we show the negative impact of technology scaling on the information-processing latency, which impacts the quality of service of an embedded ML system. At a finer granularity, the latency inside a PE depends on (1) the delay introduced by parasitic components on its current paths, and (2) the varying delay to sense different resistance states of its NVM cells. Based on these two observations, we make the following three contributions. First, on the technology front, we propose an optimization scheme where the NVM resistance state that takes the longest time to sense is set on current paths having the least delay, and vice versa, reducing the average PE latency, which improves the quality of service. Second, on the architecture front, we introduce isolation transistors within each PE to partition it into regions that can be individually power-gated, reducing both latency and energy. Finally, on the system-software front, we propose a mechanism to leverage the proposed technological and architectural enhancements when implementing an ML inference task on neuromorphic PEs of the hardware. Evaluations with a recent neuromorphic hardware architecture show that our proposed design-technology co-optimization approach improves both performance and energy efficiency of ML inference tasks without incurring high cost-per-bit.

An Adaptive Multipath Routing Method Based on Improved GA and Information Entropy

With the development of artificial intelligence technology, some emerging applications (such as computation offloading and digital twin) require higher transmission quantity and quality for wireless sensor networks (WSNs). The increasing amount of data aggravates the imbalance of node energy consumption. In the single-path routing, nodes on the optimal path consume too much energy, which leads to the premature failure of the network. In addition, the transmission protocols based on the acknowledge character (ACK) mechanism ensure the quality of service, but bring additional energy overhead. In this article, an adaptive multipath routing method based on balanced energy consumption (AMRBEC) is proposed for WSNs that significantly reduce energy consumption and prolong network lifetime. We design a new multidimensional fitness function based on the path energy, distance, hops and the lowest energy node, which servers to an improved genetic algorithm (GA) to select the multiple optimal paths. The packet loss rate is predicted by random forest to realize the non-feedback transmission. According to the residual energy and the information entropy of each path, the amount of data transmitted is dynamically adjusted, and the optimal paths are updated to balance the energy consumption of the whole network. A simulation analysis shows that the proposed AMRBEC performs better than other algorithms from the literature by improving the lifetime by 20% and reducing energy consumption by more than 20%.

Cloud–Edge Collaborative Resource Allocation for Blockchain-Enabled Internet of Things: A Collective Reinforcement Learning Approach

Driven by numerous emerging mobile devices and various Quality-of-Service (QoS) requirements, mobile-edge computing (MEC) has been recognized as a prospective paradigm to promote the computation capability of mobile devices, as well as reduce energy overhead and service latency of applications for the Internet of Things (IoT). However, there are still some open issues in the existing research works: 1) limited network and computing resource; 2) simple or nonintelligent resource management; and 3) ignored security and reliability. In order to cope with these issues, in this article, 6G and blockchain technology are considered to improve network performance and ensure the authenticity of data sharing for the MEC-enabled IoT. Meanwhile, a novel intelligent optimization method named as collective reinforcement learning (CRL) is proposed and introduced, to realize intelligent resource allocation, meet distributed training results sharing, and avoid excessive consumption of system resources. Based on the designed network model, a cloud–edge collaborative resource allocation framework is formulated. By joint optimizing the offloading decision, block interval, and transmission power, it aims to minimize the consumption overheads of system energy and latency. Then, the formulated problem is designed as a Markov decision process, and the optimal strategy can be obtained by the CRL. Some evaluation results reveal that the system performance based on the proposed scheme outperforms other existing schemes obviously.

Efficient Integrity-Tree Structure for Convolutional Neural Networks through Frequent Counter Overflow Prevention in Secure Memories.

Advancements in convolutional neural network (CNN) have resulted in remarkable success in various computing fields. However, the need to protect data against external security attacks has become increasingly important because inference process in CNNs exploit sensitive data. Secure Memory is a hardware-based protection technique that can protect the sensitive data of CNNs. However, naively applying secure memory to a CNN application causes significant performance and energy overhead. Furthermore, ensuring secure memory becomes more difficult in environments that require area efficiency and low-power execution, such as the Internet of Things (IoT). In this paper, we investigated memory access patterns for CNN workloads and analyzed their effects on secure memory performance. According to our observations, most CNN workloads intensively write to narrow memory regions, which can cause a considerable number of counter overflows. On average, 87.6% of total writes occur in 6.8% of the allocated memory space; in the extreme case, 93.9% of total writes occur in 1.4% of the allocated memory space. Based on our observations, we propose an efficient integrity-tree structure called Countermark-tree that is suitable for CNN workloads. The proposed technique reduces overall energy consumption by 48%, shows a performance improvement of 11.2% compared to VAULT-128, and requires a similar integrity-tree size to VAULT-64, a state-of-the-art technique.

Near-Optimal Energy Management for Energy Harvesting IoT Devices Using Imitation Learning

Internet of Things (IoT) devices are becoming popular in a number of transformative applications, including smart health, digital agriculture, and wide area sensing. However, small battery capacities and the need for frequent battery replacements or recharging have hindered their widespread adoption. Energy harvesting (EH) and management present a promising opportunity to enable long-term recharge free operation of IoT devices. State-of-the-art energy management approaches employ dynamic optimization methods to manage the harvested energy. However, the dynamic optimization methods are typically computationally intensive and lead to significant energy overhead for energy-constrained IoT devices. In contrast, this article proposes an imitation learning (IL)-based energy management algorithm that provides the energy budget or allocation for each decision interval without the need for dynamic optimization. We present an efficient approach to design Oracle policies that optimize the energy allocation of the IoT device to enable self-powered operation while maximizing the utility to the application. Then, we leverage the Oracle policy to train an online policy that performs near-optimal energy allocation at runtime. Our experiments with solar EH data for six years from three locations show that the proposed IL policies achieve allocation that is, on average, within 2.5 J of the Oracle, while having an energy consumption overhead of 154 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{J}$ </tex-math></inline-formula> .

PVoT: Reconfigurable Photovoltaic Array for Indoor Light Energy-Powered Batteryless Devices

Multiple photovoltaic (PV) modules are often used to provide enhanced harvesting capability for light energy-based Internet of Things (IoT) devices. PV modules facing multiple directions can lead to a situational energy loss when parts of the modules are shaded. To address this issue, existing solutions exploit reconfigurable PV arrays to acquire the optimal configuration in a given situation. However, conventional techniques are not energy efficient in estimating the harvesting capability of PV modules, and require high computation to find the optimal PV array at runtime. In this article, we propose PVoT, an energy-efficient reconfigurable PV array, which maximizes the harvesting energy for indoor IoT devices. To this end, we propose the use of photoresistors to estimate the harvesting capability with minimal energy overhead. We also provide hardware and software schemes, which perform event-driven light change detection in an energy-efficient way. Furthermore, we develop a power imbalance threshold metric to quickly find the optimal PV array at runtime. We implemented a prototype PVoT with off-the-shelf components and accompanying software. Experiments with the prototype hardware showed that PVoT achieves a gain of up to 23.9% in harvested energy compared to the existing directly connected PV array scheme.

Sorting in Memristive Memory

Sorting data is needed in many application domains. Traditionally, the data is read from memory and sent to a general-purpose processor or application-specific hardware for sorting. The sorted data is then written back to the memory. Reading/writing data from/to memory and transferring data between memory and processing unit incur significant latency and energy overhead. In this work, we develop the first architectures for in-memory sorting of data to the best of our knowledge. We propose two architectures. The first architecture is applicable to the conventional format of representing data, i.e., weighted binary radix. The second architecture is proposed for developing unary processing systems, where data is encoded as uniform unary bit-streams. As we present, each of the two architectures has different advantages and disadvantages, making one or the other more suitable for a specific application. However, the common property of both is a significant reduction in the processing time compared to prior sorting designs. Our evaluations show on average 37 × and 138× energy reduction for binary and unary designs, respectively, compared to conventional CMOS off-memory sorting systems in a 45 nm technology. We designed a 3×3 and a 5×5 Median filter using the proposed sorting solutions, which we used for processing 64×64 pixel images. Our results show a reduction of 14× and 634× in energy and latency, respectively, with the proposed binary, and 5.6× and 152×10 3 in energy and latency with the proposed unary approach compared to those of the off-memory binary and unary designs for the 3 × 3 Median filtering system.

Intelligent energy-efficient scheduling with ant colony techniques for heterogeneous edge computing

Energy efficiency is a significant issue in heterogeneous edge computing systems for a large number of latency-sensitive applications. This article presents an efficient technique to minimize energy overhead of time-constrained applications modeled by DAGs in heterogeneous edge computing. The technique is divided into three stages. First, we design a new method to compute task priority and propose the ant-colony based energy-aware scheduling algorithm to get a preliminary scheduling result. Second, taking the slack time between tasks and their deadlines into consideration, we propose the downward proportionally reclaiming slack algorithm to further cut down energy overhead by the DVFS technique. Third, taking the slack time between tasks into consideration, we propose the upward and downward proportionally reclaiming slack algorithm to cut down energy overhead by the DVFS technique again. Simulated results indicate that the presented technique is highly efficient in reducing energy overhead compared with state-of-the-art techniques using benchmarks of distinct characteristics.

Dataflow Driven Partitioning of Machine Learning Applications for Optimal Energy Use in Batteryless Systems

Sensing systems powered by energy harvesting have traditionally been designed to tolerate long periods without energy. As the Internet of Things (IoT) evolves toward a more transient and opportunistic execution paradigm, reducing energy storage costs will be key for its economic and ecologic viability. However, decreasing energy storage in harvesting systems introduces reliability issues. Transducers only produce intermittent energy at low voltage and current levels, making guaranteed task completion a challenge. Existing ad hoc methods overcome this by buffering enough energy either for single tasks, incurring large data-retention overheads, or for one full application cycle, requiring a large energy buffer. We present Julienning : an automated method for optimizing the total energy cost of batteryless applications. Using a custom specification model, developers can describe transient applications as a set of atomically executed kernels with explicit data dependencies. Our optimization flow can partition data- and energy-intensive applications into multiple execution cycles with bounded energy consumption. By leveraging interkernel data dependencies, these energy-bounded execution cycles minimize the number of system activations and nonvolatile data transfers, and thus the total energy overhead. We validate our methodology with two batteryless cameras running energy-intensive machine learning applications. Using a solar testbed, we replay real-world illuminance traces to experimentally demonstrate optimized batteryless execution with a transducer-to-application energy efficiency of 74.5%. Partitioning results demonstrate that compared to ad hoc solutions, our method can reduce the required energy storage by over 94% while only incurring a 0.12% energy overhead.

Energy optimization for deadline-constrained parallel applications on multi-ECU embedded systems

Multi-ECU (electronic control unit) systems are widely used in drones and electric vehicles. The trend of sharing resources by multiple tasks is inevitable due to the sensitive costs and space. However, the random arrival nature of tasks makes the scheduling difficult to be designed. This paper studies the task scheduling on multi-ECU embedded platforms that assume to accept more than one kind of tasks with random arrival. First, we propose an integer-linear-programming-based dynamic DAG scheduling algorithm (ILPS), which can efficiently reduce energy overheads while satisfying deadline constraints of all tasks. In addition, an offline-training-online-using strategy is proposed to speed up the generation of scheduling policies, for the use of ILPS in practice. Second, we propose a DVFS-available energy saving algorithm (DAES), which decreases energy consumption by finding an appropriate frequency for each task in an iterative manner, whilst satisfying deadline constraints. Results of extensive experiments illustrate that our algorithm is better than existing methods in terms of energy consumption and scheduling length.

Energy aware resource control mechanism for improved performance in future green 6G networks

The increasing power consumption and the energy crisis owing to several billion of connected devices raises concern. The battery powered devices or mobile terminals consume a lot of power and led to huge energy overhead. Thus, the need is to design energy sustainable networks which aims for optimum utilization of power resources. 6G enabled networks offer enhanced network coverage along with green communication capabilities and energy-aware resource management. Cell-free Massive MIMO is a promising 6G technology which offers power optimization by allowing only a subset of access points (APs) to serve a particular user. In this paper, the performance of the proposed network is evaluated for different power control methods. The average mean square error (MSE), average signal-to-noise ratio (SNR) and spectral efficiency (SE) are obtained for different users,transmit powers and pilot lengths. An efficient resource management algorithm namely, MIPA-MCAS is proposed which offers Minimum Interference Power Allocation and Maximum Channel gain AP Selection. It is observed that the spectral efficiency obtained at 95% of all user locations improves by 3.39% with the proposed algorithm. In the end, a comparative analysis is carried out with two other algorithms namely, Round-Robin Power Allocation and Maximum Channel gain AP Selection (RRPA-MCAS) and Random Power Allocation and Maximum Channel gain AP Selection (RPA-MCAS) for the proposed and conventional system models.

Nonuniform Compressive Sensing via Ohmic Voltage Attenuation: A Memristive Crossbar Design Approach Leveraging Intrinsic Computation

Compressive sensing (CS) is a promising technique for transmitting signals in power-critical applications such as Internet of Things (IoT) devices. Nonuniform CS optimizes this process by adjusting sampling frequency based on the relative importance levels characterized by the signal of interest. Recent advances have yielded energy-efficient hardware implementations of CS sampling, leveraging spin-based crossbar architectures for in-memory vector-matrix multiplication and through the use of probabilistic bit (p-bit) devices to generate tunable random outputs for writing the array. Thus, a region of interest is generated via column-ordered density of on-state devices. Herein, we propose a simple design for supplying inputs to the p-bit devices, based on Ohmic voltage attenuation occurring along the word lines of the crossbar array. The technique embeds some required computations to be conducted intrinsically by the cross-points of the memristive array, thus bypassing overheads of conventional instruction execution and eliminating the need for costly hardware components, such as lookup tables (LUTs) and data converters. The design is shown to be robust for various array sizes and parasitics while generating the appropriate tuning signals within a single clock cycle duration of 1.6 ns, and at an energy overhead of 333 fJ. Compared with a standard approach using LUTs and digital to-analog converters, the design herein achieves a 583-fold reduction in energy and 23-fold reduction in transistor count.

Adaptive Energy Management for Self-Sustainable Wearables in Mobile Health

Wearable devices that integrate multiple sensors, processors, and communication technologies have the potential to transform mobile health for remote monitoring of health parameters. However, the small form factor of the wearable devices limits the battery size and operating lifetime. As a result, the devices require frequent recharging, which has limited their widespread adoption. Energy harvesting has emerged as an effective method towards sustainable operation of wearable devices. Unfortunately, energy harvesting alone is not sufficient to fulfill the energy requirements of wearable devices. This paper studies the novel problem of adaptive energy management towards the goal of self-sustainable wearables by using harvested energy to supplement the battery energy and to reduce manual recharging by users. To solve this problem, we propose a principled algorithm referred as AdaEM. There are two key ideas behind AdaEM. First, it uses machine learning (ML) methods to learn predictive models of user activity and energy usage patterns. These models allow us to estimate the potential of energy harvesting in a day as a function of the user activities. Second, it reasons about the uncertainty in predictions and estimations from the ML models to optimize the energy management decisions using a dynamic robust optimization (DyRO) formulation. We propose a light-weight solution for DyRO to meet the practical needs of deployment. We validate the AdaEM approach on a wearable device prototype consisting of solar and motion energy harvesting using real-world data of user activities. Experiments show that AdaEM achieves solutions that are within 5% of the optimal with less than 0.005% execution time and energy overhead.

Split PO for paging in B5G networks

Beyond 5G (B5G) wireless networks, imbued with several beams to support high-frequency spectrum, would require enhancements to the current paging monitoring mechanism in Idle mode Discontinuous Reception (IDRX) for improving UE’s energy efficiency. The lengthy pre-wakeup and processing overheads in directional IDRX for beam tracking and time–frequency synchronization in every IDRX cycle would result in higher UE’s power consumption. Recently, the functioning of Synchronization Signal Block (SSB) has been standardized for synchronization in New Radio (NR) 5G communications. In this article we first highlight inevitability and details of SSB measurements in every IDRX cycle of directional 5G/B5G communication. The UE’s power saving reduces substantially due to SSB measurements as the deep sleep duration in every IDRX cycle shrinks. Moreover, during the time gap between periodic SSB transmission(s), the UE can only transit to light sleep. An early indication that can inform UE whether to measure multiple SSB’s when paging is expected in an IDRX cycle or continue to deep sleep in absence of paging would be very beneficial in UE’s power saving. We propose a novel Split PO Paging (SPOP) mechanism that manifests early indication, avoids unnecessary SSB measurements and reduces UE’s pre-wakeup energy overheads. We use Markov chain modeling to analyze SPOP and validate our modeling through simulations. The Proposed SPOP can save more than 40% power compared to IDRX mechanism with elaborate pre wake-up and processing.

Linear Error Correction Codec Implementation Based on an In-Memory Computing Architecture for Nonvolatile Memories

Nonvolatile memories (NVMs) have been widely studied in the post-Moore era. However, noise/defect in NVMs has brought a challenging reliability problem in write/read access operations. A linear error correction code (ECC) has been widely used in memories to correct errors. In general, a codec hardware is required to encode or decode the information, resulting in area and energy overhead. In this article, we propose a new approach to implement the ECC codec by exploiting the existing write and read peripheral circuitry of NVMs based on an in-memory computing (IMC) architecture. In our approach, the desired code words can be generated through using write-like logic operations, given the original information and generation matrix during the encoding (write) process, while syndrome vectors (or error correction) can also be achieved through using read-like logic operations, given the parity-check matrix during the decoding (read) process, respectively. Therefore, we do not need a specific codec hardware but exploit the write-like and read-like logic operations. With an emerging toggle spin torque magnetic random access memory (TST-MRAM) and Hamming code as an example, we validated the feasibility of our approach and evaluated the performance of the design in the 40-nm technology node. The results show that our approach can significantly reduce energy consumption compared with state-of-the-art designs.

An FPGA-based Approach to Evaluate Thermal and Resource Management Strategies of Many-core Processors

The continuous technology scaling of integrated circuits results in increasingly higher power densities and operating temperatures. Hence, modern many-core processors require sophisticated thermal and resource management strategies to mitigate these undesirable side effects. A simulation-based evaluation of these strategies is limited by the accuracy of the underlying processor model and the simulation speed. Therefore, we present, for the first time, an field-programmable gate array (FPGA)-based evaluation approach to test and compare thermal and resource management strategies using the combination of benchmark generation, FPGA-based application-specific integrated circuit (ASIC) emulation, and run-time monitoring. The proposed benchmark generation method enables an evaluation of run-time management strategies for applications with various run-time characteristics. Furthermore, the ASIC emulation platform features a novel distributed temperature emulator design, whose overhead scales linearly with the number of integrated cores, and a novel dynamic voltage frequency scaling emulator design, which precisely models the timing and energy overhead of voltage and frequency transitions. In our evaluations, we demonstrate the proposed approach for a tiled many-core processor with 80 cores on four Virtex-7 FPGAs. Additionally, we present the suitability of the platform to evaluate state-of-the-art run-time management techniques with a case study.