Energy-efficient Computing Research Articles

Design and performance investigation of tunnel-FET based energy efficient approximate and accurate adders targeted towards low power IoT nodes

Abstract The proliferation of IoT enabled SoCs in state-of-the-art consumer electronics has necessitated the use of beyond CMOS devices for the energy efficient computations and sensing design space. In the low supply voltage (VDD) regime, Tunnel FETs (TFETs) have shown serious potential at VDD less than 0.5 V. However, the inherent structure, characteristic interband tunneling and enhance Miller capacitance in TFETs do not allow the conventional CMOS logic design styles to be universally used for TFET based logic circuits. In this paper, we propose three energy efficient and novel TFET based accurate adder circuits namely, Static Energy Recovery Full adder (SERF), Complementary and Level Restoring Carry Logic Full adder (CLRCL) and Balanced Restoring Carry Logic full adder (BRCL) based on constituent TFET based functional units which do not use the CMOS design style. Further, novel approximate adders have been developed for energy efficient implementation in IoT nodes. The BRCL adder consumes approximately 60% less area and 85.36% and 89.6% less energy in comparison to SERF and CLRCL respectively. The approximate adders in the best and worst case facilitate approximately 92% and 75% savings in area and consumes 71% less power than the BRCL adder. When compared to the standard UMC 45 nm bulk MOSFET based designs, the TFET based accurate adders operate at 25% less energy while the approximate adders consume 40% less. All the circuit simulations have been performed using Spectre Simulator of Cadence and device characterization using 2D-TCAD tool.

Evolution of computing energy efficiency: Koomey's law revisited

For information and communication technology power consumption to be sustainable, the energy efficiency of computing systems must grow at least as fast as the demand for computing services. It is therefore crucial to understand how energy efficiency is evolving and how it will trend in the future, in order to take appropriate measures where possible. This article analyses the evolution of this parameter by analysing high-performance computers from 2008 to 2023, contrasting the results with those from Koomey's Law. It is concluded, after comparing the two that in the studied period and in the near future, energy efficiency continues to grow exponentially but at a slower rate than that established by Koomey's Law (maximum energy efficiency doubles every 2.29 years instead of every 1.57 years). Another interesting result is that energy efficiency grows at a slower rate (doubling every 2.29 years) than performance (doubling every 1.85 years).

Spin-torque nano-oscillators and their applications

Spin-torque nano-oscillators (STNOs) have emerged as an intriguing category of spintronic devices based on spin transfer torque to excite magnetic moment dynamics. The ultra-wide frequency tuning range, nanoscale size, and rich nonlinear dynamics have positioned STNOs at the forefront of advanced technologies, holding substantial promise in wireless communication, and neuromorphic computing. This review surveys recent advances in STNOs, including architectures, experimental methodologies, magnetodynamics, and device properties. Significantly, we focus on the exciting applications of STNOs, in fields ranging from signal processing to energy-efficient computing. Finally, we summarize the recent advancements and prospects for STNOs. This review aims to serve as a valuable resource for readers from diverse backgrounds, offering a concise yet comprehensive introduction to STNOs. It is designed to benefit newcomers seeking an entry point into the field and established members of the STNOs community, providing them with insightful perspectives on future developments.

120 GOPS Photonic tensor core in thin-film lithium niobate for inference and in situ training

Photonics offers a transformative approach to artificial intelligence (AI) and neuromorphic computing by enabling low-latency, high-speed, and energy-efficient computations. However, conventional photonic tensor cores face significant challenges in constructing large-scale photonic neuromorphic networks. Here, we propose a fully integrated photonic tensor core, consisting of only two thin-film lithium niobate (TFLN) modulators, a III-V laser, and a charge-integration photoreceiver. Despite its simple architecture, it is capable of implementing an entire layer of a neural network with a computational speed of 120 GOPS, while also allowing flexible adjustment of the number of inputs (fan-in) and outputs (fan-out). Our tensor core supports rapid in-situ training with a weight update speed of 60 GHz. Furthermore, it successfully classifies (supervised learning) and clusters (unsupervised learning) 112 × 112-pixel images through in-situ training. To enable in-situ training for clustering AI tasks, we offer a solution for performing multiplications between two negative numbers.

Compact Physical Implementation of Spiking Neural Network Using Ambipolar WSe2 n-Type/p-Type Ferroelectric Field-Effect Transistor.

Spiking neural networks (SNNs) are attracting increasing interests for their ability to emulate biological processes, offering energy-efficient computation and event-driven processing. Currently, no devices are known to combine both neuronal and synaptic functions. This study presents an experimental demonstration of an ambipolar WSe2 n-type/p-type ferroelectric field-effect transistor (n/p-FeFET) integrated with ferroelectric Hf0.5Zr0.5O2 (HZO) to achieve both volatile and nonvolatile properties in a single device. The nonvolatile n-FeFET, driven by the stable ferroelectric properties of HZO, exhibits highly linear synaptic behavior. In contrast, the volatile p-FeFET, influenced by electron self-compensation in the ambipolar WSe2, enables self-resetting leaky-integrate-and-fire neurons. Integrating neuronal and synaptic functions in the same device allows for compact neuromorphic computing applications. Additionally, simulations of SNNs using experimentally calibrated synaptic and neuronal models achieved a 93.8% accuracy in MNIST digit recognition. This innovative approach advances the development of SNNs with high biomimetic fidelity and reduced hardware costs.

Implementation of Artificial Neural Networks on Field-Programmable Gate Arrays

Implementing Artificial Neural Networks (ANNs) on Field-Programmable Gate Arrays (FPGAs) provides a promising solution for achieving high-performance, low-latency, and energy-efficient computations in complex tasks. This paper investigates the methodology for mapping ANNs onto FPGAs, focusing on critical aspects such as architecture selection, hardware design, and optimization techniques. By harnessing the parallel processing capabilities and reconfigurability of FPGAs, neural network computations are significantly accelerated, making them ideal for real-time applications like image processing and embedded systems. The implementation process addresses key considerations, including fixed-point arithmetic, memory management, and dataflow optimization, while employing advanced techniques such as pipelining, quantization, and pruning. The research compares the accuracy and performance speedup of ANNs on CPUs versus FPGAs, revealing that FPGA-based simulations are 4680 times faster than CPU-based simulations using MATLAB, without compromising prediction accuracy.

Learning long sequences in spiking neural networks

Spiking neural networks (SNNs) take inspiration from the brain to enable energy-efficient computations. Since the advent of Transformers, SNNs have struggled to compete with artificial networks on modern sequential tasks, as they inherit limitations from recurrent neural networks (RNNs), with the added challenge of training with non-differentiable binary spiking activations. However, a recent renewed interest in efficient alternatives to Transformers has given rise to state-of-the-art recurrent architectures named state space models (SSMs). This work systematically investigates, for the first time, the intersection of state-of-the-art SSMs with SNNs for long-range sequence modelling. Results suggest that SSM-based SNNs can outperform the Transformer on all tasks of a well-established long-range sequence modelling benchmark. It is also shown that SSM-based SNNs can outperform current state-of-the-art SNNs with fewer parameters on sequential image classification. Finally, a novel feature mixing layer is introduced, improving SNN accuracy while challenging assumptions about the role of binary activations in SNNs. This work paves the way for deploying powerful SSM-based architectures, such as large language models, to neuromorphic hardware for energy-efficient long-range sequence modelling.

Энергоэффективность многоядерных процессоров: сравнительное исследование аппаратных технологий

Background: The constant increase in processing demand has prompted the development of multi-core processors, which are critical to obtaining high performance in a variety of computing devices. However, this growth in processing capacity comes at the expense of increased energy consumption, posing substantial problems for energy efficiency. Objective: The article will examine and compare several hardware solutions for improving energy efficiency in multi-core processors, offering a full overview of their effectiveness and application. Methods: We used a quantitative research methodology, simulating multi-core processing environments with various hardware optimization techniques such as Dynamic Voltage and Frequency Scaling (DVFS), Clock Gating, and Power Gating. Each technique was evaluated in a variety of operational circumstances to establish its effect on energy consumption and processing efficiency. Results: The findings show that DVFS provides significant energy savings with negligible performance trade-offs in cases with moderate workloads. In contrast, Clock Gating performed best in low workload settings, whereas Power Gating performed best in high-load conditions, dramatically reducing idle power consumption. Conclusion: The comparison research demonstrates that no single technique beats all others; rather, the choice of an effective energy efficiency strategy is significantly influenced by unique workload factors. A hybrid strategy, which combines both techniques depending on real-time workload demands, can greatly improve the energy efficiency of multi-core processors. This study advances our understanding of energy management in advanced computing systems, providing insights for future research and practical applications in the field of energy-efficient computing.

Second-order mean-field approximation for calculating dynamics in Au-nanoparticle networks.

Exploiting physical processes for fast and energy-efficient computation bears great potential in the advancement of modern hardware components. This paper explores nonlinear charge tunneling in nanoparticle networks, controlled by external voltages. The dynamics are described by a master equation, which expresses the time-evolution of a distribution function over the set of charge occupation numbers. The driving force behind this evolution is charge tunneling events among nanoparticles and their associated rates. We introduce two mean-field approximations to this master equation. By parametrization of the distribution function using its first- and second-order statistical moments, and a subsequent projection of the dynamics onto the resulting moment manifold, one can deterministically calculate expected charges and currents. Unlike a kinetic Monte Carlo approach, which extracts samples from the distribution function, this mean-field approach avoids any random elements. A comparison of results between the mean-field approximation and an already available kinetic Monte Carlo simulation demonstrates great accuracy. Our analysis also reveals that transitioning from a first-order to a second-order approximation significantly enhances the accuracy. Furthermore, we demonstrate the applicability of our approach to time-dependent simulations, using Eulerian time-integration schemes.

Tuning high-level synthesis SpMV kernels in Alveo FPGAs

Sparse Matrix-Vector Multiplication (SpMV) is an essential operation in scientific and engineering fields, with applications in areas like finite element analysis, image processing, and machine learning. To address the need for faster and more energy-efficient computing, this paper investigates the acceleration of SpMV through Field-Programmable Gate Arrays (FPGAs), leveraging High-Level Synthesis (HLS) for design simplicity. Our study focuses on the AMD-Xilinx Alveo U280 FPGA, assessing the performance of the SpMV kernel from Vitis Libraries, which is the state of the art on SpMV acceleration on FPGAs. We explore kernel modifications, transition to single precision, and varying partition sizes, demonstrating the impact of these changes on execution time. Furthermore, we investigate matrix preprocessing techniques, including Reverse Cuthill-McKee (RCM) reordering and a hybrid sparse storage format, to enhance efficiency. Our findings reveal that the performance of FPGA-accelerated SpMV is influenced by matrix characteristics, by smaller partition sizes, and by specific preprocessing techniques delivering notable performance improvements. By selecting the best results from these experiments, we achieved execution time enhancements of up to 3.2×. This study advances the understanding of FPGA-accelerated SpMV, providing insights into key factors that impact performance and potential avenues for further improvement.

Solving Boltzmann optimization problems with deep learning

Decades of exponential scaling in high-performance computing (HPC) efficiency is coming to an end. Transistor-based logic in complementary metal-oxide semiconductor (CMOS) technology is approaching physical limits beyond which further miniaturization will be impossible. Future HPC efficiency gains will necessarily rely on new technologies and paradigms of computing. The Ising model shows particular promise as a future framework for highly energy-efficient computation. Ising systems are able to operate at energies approaching thermodynamic limits for energy consumption of computation. Ising systems can function as both logic and memory. Thus, they have the potential to significantly reduce energy costs inherent to CMOS computing by eliminating costly data movement. The challenge in creating Ising-based hardware is in optimizing useful circuits that produce correct results on fundamentally nondeterministic hardware. The contribution of this paper is a novel machine learning approach, a combination of deep neural networks and random forests, for efficiently solving optimization problems that minimize sources of error in the Ising model. In addition, we provide a process to express a Boltzmann probability optimization problem as a supervised machine learning problem.

Reducing the spike rate of deep spiking neural networks based on time-encoding

A primary objective of Spiking Neural Networks is a very energy-efficient computation. To achieve this target, a small spike rate is of course very beneficial given the event-driven nature of such a computation. A network that processes information encoded in spike timing can, by its nature, have such a sparse event rate, but, as the network becomes deeper and larger, the spike rate tends to increase without any improvements in the final accuracy. If, on the other hand, a penalty on the excess of spikes is used during the training, the network may shift to a configuration where many neurons are silent, thus affecting the effectiveness of the training itself. In this paper, we present a learning strategy to keep the final spike rate under control by changing the loss function to penalize the spikes generated by neurons after the first ones. Moreover, we also propose a 2-phase training strategy to avoid silent neurons during the training, intended for benchmarks where such an issue can cause the switch off of the network.

Exploring the trade-off between computational power and energy efficiency: An analysis of the evolution of quantum computing and its relation to classical computing

Quantum computing is considered a revolutionary technology due to its ability to solve computational problems that are beyond the capabilities of classical computers. However, quantum computing requires great amounts of energy to run. Therefore, a factor in deciding whether to use quantum computing should be not only the complexity of the problem to be solved, but also the energy required to solve it. This paper presents an empirical study developed with the aim of comparing classical and quantum computing in terms of energy efficiency to determine whether the increased power of quantum computers is offset by their higher energy consumption. To achieve this, a variety of problems with different levels of complexity were tested on both types of computers. Specifically, we used the IBM Quantum computers with a maximum of 5 qubits and an Intel i7, as a classical computer. In addition to this we have also analysed the evolution of the quantum computers, performing measurements on three time periods. Our empirical study showed that there is a variability of results obtained in the three time periods and that quantum computing is not recommended for low-complexity problems, given its high energy consumption, particularly when compared to traditional computing.

Computational elements based on coupled VO2 oscillators via tunable thermal triggering

Computational technologies based on coupled oscillators are of great interest for energy efficient computing. A key to developing such technologies is the tunable control of the interaction among oscillators which today is accomplished by additional electronic components. Here we show that the synchronization of closely spaced vanadium dioxide (VO2) oscillators can be controlled via a simple thermal triggering element that itself is formed from VO2. The net energy consumed by the oscillators is lower during thermal coupling compared with the situation where they are oscillating independently. As the size of the oscillator shrinks from 6 μm to 200 nm both the energy efficiency and the oscillator frequency increases. Based on such oscillators with active tuning, we demonstrate AND, NAND, and NOR logic gates and various firing patterns that mimic the behavior of spiking neurons. Our findings demonstrate an innovative approach towards computational techniques based on networks of thermally coupled oscillators.

Hardware Implementation of Next Generation Reservoir Computing with RRAM‐Based Hybrid Digital‐Analog System

Reservoir computing (RC) possesses a simple architecture and high energy efficiency for time‐series data analysis through machine learning algorithms. To date, RC has evolved into several innovative variants. The next generation reservoir computing (NGRC) variant, founded on nonlinear vector autoregression (NVAR) distinguishes itself due to its fewer hyperparameters and independence from physical random connection matrices, while yielding comparable results. However, NGRC networks struggle with massive Kronecker product calculations and matrix‐vector multiplications within the read out layer, leading to substantial efficiency challenges for traditional von Neumann architectures. In this work, a hybrid digital‐analog hardware system tailored for NGRC is developed. The digital part is a Kronecker product calculation unit with data filtering, which realizes transformation of nonlinear vector of the input linear vector. For matrix‐vector multiplication, a computing‐in‐memory architecture based on resistive random access memory array offers an energy‐efficient hardware solution, which markedly reduces data transfer and greatly improve computational parallelism and energy efficiency. The predictive capabilities of this hybrid NGRC system are validated through the Lorenz63 model, achieving a normalized root mean square error (NRMSE) of 0.00098 and an energy efficiency of 19.42TOPS W−1.

Readout Circuit Design for RRAM Array-Based Computing in Memory Architecture

In recent advancements, the traditional von Neumann architecture has been challenged by the computational needs of AI. This is due to its high power and data transfer costs. As a solution, the computing-in-memory (CIM) architecture, which combines storage and computation, has gained attention for its superior computational power and energy efficiency. Within CIM, using resistive random access memory (RRAM) arrays, the readout circuit, which converts analog outputs from multiply–accumulate operations into digital signals, faces limitations due to its area and power consumption. There are mainly two types of CIM readout circuits for analog types: the traditional ADC type and the non-traditional type. This paper presents two types of readout circuit designs. The first is a low-power, compact successive approximation register (SAR) analog-to-digital converter (ADC) readout circuit. The core circuit is an 8-bit SAR ADC operating at 70 MS/s. It incorporates a linearity-improved bootstrapped switch to minimize leakage and enhance linearity, whose spurious-free dynamic range (SFDR) has been improved by 10.1 dB from 76.78 dB to 86.88 dB, and whose signal-to-noise and distortion ratio (SNDR) has increased by 4.56 dB from 75.13 dB to 79.69 dB. The delay of a transconductance-enhanced dynamic comparator is reduced from 184 ps to 149 ps, presenting a performance improvement of approximately 20%. Concurrently, the energy consumption decreased from 178 μm to 132 μm, attaining an improvement of roughly 26%. A “sandwich” capacitor structure is used that reduces the overall area of the layout. After layout and post-simulation, this circuit occupies only 49.6 μm × 51.5 μm, consumes 553 μW power, has a SINAD of 46.22 dB, and has an SFDR of 57.21 dB. The second is a current controlled oscillator (CCO)-type readout circuit, which comprises a CCO oscillator with low process-sensitivity. The readout circuit also utilizes an op-amp and current mirrors for a negative feedback loop, ensuring a constant voltage across the RRAM arrays. The frequency generated through the CCO is controlled by the current, and quantified by a counter, supporting different weights quantification per ReRAM column without additional digital weighting. This circuit achieves 95-level resolution, 5.2 μs delay, and an average consumption of 183.1 μW. A comparative analysis highlights that traditional ADC readout circuits offer high resolution and speed but are limited by their high power and area costs, often overshadowing CIM arrays’ benefits. Thus, for applications with more lenient resolution and speed requirements, non-traditional readout circuits present considerable advantages.

Competition of decoherence and quantum speed limits for quantum-gate fidelity in the Jaynes-Cummings model

Quantum computers are operated by external driving fields, such as lasers, microwaves, or transmission lines, that execute logical operations on multiqubit registers, leaving the system in a pure state. However, the drive and the logical system might become correlated in such a way that, after tracing out the degrees of freedom of the driving field, the output state will not be pure. Previous works have pointed out that the resulting error scales inversely with the energy of the drive, thus imposing a limit on the energy efficiency of quantum computing. In this study, focusing on the Jaynes-Cummings model, we show how the same scaling can be seen as a consequence of two competing phenomena: the entanglement-induced error, which grows with time, and a minimal time for computation imposed by quantum speed limits. This evidence is made possible by quantifying, at any time, the computation error via the spectral radius associated with the density operator of the logical qubit. Moreover, we also prove that, in order to attain a given target state at a chosen fidelity, it is energetically more efficient to perform a single driven evolution of the logical qubits rather than to split the computation in subroutines, each operated by a dedicated pulse. Published by the American Physical Society 2024

Charge Trapping and Defect Dynamics as Origin of Memory Effects in Metal Halide Perovskite Memlumors.

Large language models for artificial intelligence applications require energy-efficient computing. Neuromorphic photonics has the potential to reach significantly lower energy consumption in comparison with classical electronics. A recently proposed memlumor device uses photoluminescence output that carries information about its excitation history via the excited state dynamics of the material. Solution-processed metal halide perovskites can be used as efficient memlumors. We show that trapping of photogenerated charge carriers modulated by photoinduced dynamics of the trapping states themselves explains the memory response of perovskite memlumors on time scales from nanoseconds to minutes. The memlumor concept shifts the paradigm of the detrimental role of charge traps and their dynamics in metal halide perovskite semiconductors by enabling new applications based on these trap states. The appropriate control of defect dynamics in perovskites allows these materials to enter the field of energy-efficient photonic neuromorphic computing, which we illustrate by proposing several possible realizations of such systems.

Computation Energy Efficiency Maximization for NOMA-Based and Wireless-Powered Mobile Edge Computing With Backscatter Communication

Computation Energy Efficiency Maximization for NOMA-Based and Wireless-Powered Mobile Edge Computing With Backscatter Communication

Approaching the Ideal Linearity in Epitaxial Crystalline-Type Memristor by Controlling Filament Growth.

Brain-inspired neuromorphic computing has attracted widespread attention owing to its ability to perform parallel and energy-efficient computation. However, the synaptic weight of amorphous/polycrystalline oxide based memristor usually exhibits large nonlinear behavior with high asymmetry, which aggravates the complexity of peripheral circuit system. Controllable growth of conductive filaments is highly demanded for achieving the highly linear conductance modulation. However, the stochastic behavior of the filament growth in commonly used amorphous/polycrystalline oxide memristor makes it very challenging. Here, the epitaxially grown Hf0.5Zr0.5O2-based memristor with the linearity and symmetry approaching ideal case is reported. A layer of Cu nanoparticles is inserted into epitaxially grown Hf0.5Zr0.5O2 film to form the grain boundaries due to the breaking of the epitaxial growth. By combining with the local electric field enhancement, the growth of filament is confined in the grain boundaries due to the fact that the diffusion of oxygen vacancy in crystalline lattice is more difficult than that in the grain boundaries. Furthermore, the decimal operation and high-accuracy neural network are demonstrated by utilizing the highly linear and multi-level conductance modulation capacity. This method opens an avenue to control the filament growth for the application of resistance random access memory (RRAM) and neuromorphic computing.