Energy-efficient Computing Research Articles

Dynamic offloading strategy for computational energy efficiency of wireless power transfer based MEC networks in industry 5.0

Wireless power transfer (WPT) has emerged as a promising solution for delivering services to low-power Internet of Things (IoT) devices in a demand-driven manner. In this work, we consider the Wireless power-enabled Hybrid Mobile Edge Cloud (WPHMEC) network, which utilizes a dynamic offloading strategy (partial and binary) to maximize computational efficiency while minimizing device energy consumption. To address this challenge, we formulate a convex optimization problem to maximize the number of computational bits and minimize the energy consumption of the IIoT devices in the WPT-based MEC system for Industry 5.0 applications. To achieve this goal, we employ a reformulation approach based on block coordinate descent (BCD) to formulate an optimization problem that addresses the nonconvexity of the problem and propose a solution approach using the Karush–Kuhn–Tucker (KKT) conditions. To validate the effectiveness of the proposed scheme, extensive simulations are carried out using the Matlab software to evaluate the system’s performance and components. The results demonstrate that optimal resource allocation maximizes energy efficiency and enhances computational resource utilization, making WPHMEEC an ideal choice for addressing the evolving demands of Industry 5.0 applications.

Exploring energy saving opportunities in fault tolerant HPC systems

Nowadays, improving the energy efficiency of high-performance computing (HPC) systems is one of the main drivers in scientific and technological research. As large-scale HPC systems require some fault-tolerant method, the opportunities to reduce energy consumption should be explored. In particular, rollback-recovery methods using uncoordinated checkpoints prevent all processes from re-executing when a failure occurs. In this context, it is possible to take actions to reduce the energy consumption of the nodes whose processes do not re-execute. This work is an extension of a previous one, in which we proposed a series of strategies to manage energy consumption at failure-time. In this work, we have enriched our simulator and the experimentation by including non-blocking communications (with and without system buffering) and a largest number of candidate processes to be analyzed. We have called the latter as cascade analysis, because it includes processes that gets blocked by communication indirectly with the failed process. The simulations show that the savings were negligible in the worst case, but in some scenarios, it was possible to achieve significant ones; the maximum saving achieved was 90% in a time interval of 16 minutes. As a result, we show the feasibility of improving energy efficiency in HPC systems in the presence of a failure.

Power efficient MoS2 synaptic devices based on Maxwell–Wagner interfacial charging in binary oxides

Synaptic devices with tunable weight hold great promise in enabling non-von Neumann architecture for energy efficient computing. However, conventional metal-insulator-metal based two-terminal memristors share the same physical channel for both programming and reading, therefore the programming power consumption is dependent on the synaptic resistance states and can be particularly high when the memristor is in the low resistance states. Three terminal synaptic transistors, on the other hand, allow synchronous programming and reading and have been shown to possess excellent reliability. Here we present a binary oxide based three-terminal MoS2 synaptic device, in which the channel conductance can be modulated by interfacial charges generated at the oxide interface driven by Maxwell-Wagner instability. The binary oxide stack serves both as an interfacial charge host and gate dielectrics. Both excitatory and inhibitory behaviors are experimentally realized, and the presynaptic potential polarity can be effectively controlled by engineering the oxide stacking sequence, which is a unique feature compared with existing charge-trap based synaptic devices and provides a new tuning knob for controlling synaptic device characteristics. By adopting a three-terminal transistor structure, the programming channel and reading channel are physically separated and the programming power consumption can be kept constantly low (∼50 pW) across a wide dynamic range of 105. This work demonstrates a complementary metal oxide semiconductor compatible approach to build power efficient synaptic devices for artificial intelligence applications.

Research on the current compensation mechanism of FJTL in ERSFQ

Energy-efficient rapid single flux quantum (ERSFQ) devices have unique energy advantages with a power consumption of less than 0.001fJ per single-bit switch, even considering the energy required for the refrigeration system, achieving ultra-low energy consumption of sub-fJ/bit. Combined with its typical operating frequency in the tens of GHz range, ERSFQ circuits have the potential to realize computing chips with extremely high computational power and energy efficiency, making them highly promising for applications in the post-Moore era. However, the performance improvement of ERSFQ circuits faces two challenges. One is how to reduce the size of their feeding Josephson transmission line (FJTL), which is required to stabilize the voltage bias of the ERSFQ circuits. The second challenge is how to improve their bias margin. The measured bias margin of ERSFQ circuits is relatively smaller than for Rapid Single Flux Quantum (RSFQ) circuits. This study investigates the current compensation mechanism of the FJTL and derives a formula for the compensating current ΔI in the main logic circuit by each pulse input to the FJTL. Based on the formula, a method is proposed to enhance the bias margin of ERSFQ circuits while reducing the size of FJTL by applying feeding pulses into the FJTL. We applied this method to an 8-bit ERSFQ shift register (SR), where the size of its FJTL is 4 JTLs (each JTL consists of 2 Josephson junctions). The measurement demonstrated an improvement of the bias margin from [84 %, 104 %] to [38 %, 104 %], confirming the feasibility of the proposed method. Furthermore, by comparing the measurement results of an 8-bit ERSFQ SR, where the size of its FJTL is 6 JTLs, it is demonstrated that applying this method can also reduce the size of the FJTL while maintaining a large margin.

EMSN: An Energy-Efficient Memristive Sequencer Network for Human Emotion Classification in Mental Health Monitoring

Mental health problems are an increasingly common social issue severely affecting health and well-being. Multimedia processing technologies via facial expression show appealing prospects in the consumer field for mental health monitoring, while still suffer from intensive computation and low energy efficiency. This paper proposes an energy-efficiency memristive sequencer network (EMSN) for human emotion classification, which offers an environmentally friendly approach for consumers with low cost and easily deployable hardware. Firstly, two-dimensional (2D) materials are employed to construct an eco-friendly memristor, the efficacy and reliability of which are confirmed through performance testing. Then, a sequencer block is proposed using memristive circuits. Notably, it is a core component of the EMSN, consisting of a bidirectional long short-term memory circuit, normalisation circuit module, and multi-layer perception module. After combining some necessary function modules, the EMSN can be achieved. Furthermore, the proposed EMSN is applied for human emotion classification. The experimental results demonstrate that the proposed EMSN has advantages in computational efficiency and classification accuracy compared to existing mainstream methods, indicating an advancement in consumer health monitoring.

MNSIM 2.0: A Behavior-Level Modeling Tool for Processing-In-Memory Architectures

In the age of Artificial Intelligence (AI), the huge data movements between memory and computing units become the bottleneck of von Neumann architectures, i.e., the “memory wall” problem. In order to tackle this challenge, Processing-In-Memory (PIM) architectures are proposed, which perform in-situ computations in memory and give alternative solutions to boost the computing energy efficiency and performance. Because of the large-scale Neural Network (NN) algorithm models and the huge hardware design space, various factors affect computing accuracy and performance, bringing the need for efficient PIM modeling and evaluation tools. In this work, we propose a behavior-level modeling tool, MNSIM 2.0, to model the performance of PIM architectures efficiently. At the hardware level, MNSIM 2.0 provides a hierarchical PIM modeling structure with flexible architecture configurability and components extensibility. Moreover, the first unified PIM memory array model is proposed for describing both digital and analog PIM. At the algorithm level, MNSIM 2.0 supports the PIM-based NN computing accuracy simulation considering various architecture and device parameters. A PIM-oriented NN model training and quantization flow is also integrated to improve the performance gain brought by PIM. At the scheduling level, MNSIM 2.0 adopts a universal scheduling description compatible with different scheduling strategies. Validation using fabricated PIM macros shows the relative modeling error rate of MNSIM 2.0 is 3:8 5:5%. Case studies show that MNSIM 2.0 enables PIM design space explorations, influences analysis of device parameters, and architecture design insight discoveries.

Classical half-adder using trapped-ion quantum bits: Toward energy-efficient computation

Reversible computation has been proposed as a future paradigm for energy efficient computation, but so far few implementations have been realized in practice. Quantum circuits, running on quantum computers, are one construct known to be reversible. In this work, we provide a proof-of-principle of classical logical gates running on quantum technologies. In particular, we propose and realize experimentally, Toffoli and Half-Adder circuits suitable for classical computation, using radio frequency-controlled 171Yb+ ions in a macroscopic linear Paul-trap as qubits. We analyze the energy required to operate the logic gates, both theoretically and experimentally, with a focus on the control energy. We identify bottlenecks and possible improvements in future platforms for energetically efficient computation, e.g., trap chips with integrated antennas and cavity qed. Our experimentally verified energetic model also fills a gap in the literature of the energetics of quantum information and outlines the path for its detailed study, as well as its potential applications to classical computing.

Addressable superconductor integrated circuit memory from delay lines

Recent advances in logic schemes and fabrication processes have renewed interest in using superconductor electronics for energy-efficient computing and quantum control processors. However, scalable superconducting memory still poses a challenge. To address this issue, we present an alternative to approaches that solely emphasize storage cell miniaturization by exploiting the minimal attenuation and dispersion properties of superconducting passive transmission lines to develop a delay-line memory system. This fully superconducting design operates at speeds between 20 and 100 GHz, with ± 24% and ± 13% bias margins, respectively, and demonstrates data densities in the 10s of Mbit/cm2 with the MIT Lincoln Laboratory SC2 fabrication process. Additionally, the circulating nature of this design allows for minimal control circuitry, eliminates the need for data splitting and merging, and enables inexpensive implementations of sequential access and content-addressable memories. Further advances in fabrication processes suggest data densities of 100s of Mbit/cm2 and beyond.

Energy efficient computing by using of software optimization aimed on execution time

Despite of all hardware capabilities, optimization of software always was one of actual tasks. Usually optimization of software was aimed to reduce an execution time. But recent decades it’s possible sometimes also to reduce energy consumption and/or energy efficiency of computing because of enhanced energy saving capabilities. Indeed, if computations are made faster, CPU can suspend unusual computational and control blocks. In case of parallelization which is one of optimization techniques, power consumption can raise in short periods of computations because of using multiple CPUs simultaneously. At once execution time can be decreased dramatically so energy efficiency of computing still increasing. In the paper the authors provide the experiments on small size mini PC Raspberry Pi 3B which show that using of optimization tiling method not only speed up a processing but also increase energy efficiency of computing. For such low power systems this can be useful to increase power on time with a battery power source.

(Invited) Physical Understanding of HfZrO2/Si FeFET Memory and Its AI Applications

Si-friendly HfO2-based FeFETs have been well recognized as a technology booster for future integrated memory applications, which are expected to enhance the energy efficiency of AI computation. In this paper, we present our recent studies on the understanding of the coupling between polarization, inversion-layer charges, and carrier traps in HfZrO2 (HZO)/Si FeFET memory. Discrimination of polarization, inversion carriers, and trapped carriers is realized by combining P-V, quasi-split C-V, and Hall measurements of FeFETs. Polarization and electron/hole-trap interactions significantly affect the performance and characteristics of HZO/Si FeFETs. A large number of electron traps can enhance polarization and the memory window of n-FeFETs, while there are almost no hole traps, leading to the smaller memory window of p-FeFETs. We have also proposed a new scheme of physical reservoir computing with parallel data processing for speech recognition by using HZO/Si FeFETs. A high classification accuracy of 95.9 % has been experimentally demonstrated in the task to classify the audio waveforms of ‘0’ to ‘9’ spoken digits.

ALBSNN: ultra-low latency adaptive local binary spiking neural network with accuracy loss estimator.

Spiking neural network (SNN) is a brain-inspired model with more spatio-temporal information processing capacity and computational energy efficiency. However, with the increasing depth of SNNs, the memory problem caused by the weights of SNNs has gradually attracted attention. In this study, we propose an ultra-low latency adaptive local binary spiking neural network (ALBSNN) with accuracy loss estimators, which dynamically selects the network layers to be binarized to ensure a balance between quantization degree and classification accuracy by evaluating the error caused by the binarized weights during the network learning process. At the same time, to accelerate the training speed of the network, the global average pooling (GAP) layer is introduced to replace the fully connected layers by combining convolution and pooling. Finally, to further reduce the error caused by the binary weight, we propose binary weight optimization (BWO), which updates the overall weight by directly adjusting the binary weight. This method further reduces the loss of the network that reaches the training bottleneck. The combination of the above methods balances the network's quantization and recognition ability, enabling the network to maintain the recognition capability equivalent to the full precision network and reduce the storage space by more than 20%. So, SNNs can use a small number of time steps to obtain better recognition accuracy. In the extreme case of using only a one-time step, we still can achieve 93.39, 92.12, and 69.55% testing accuracy on three traditional static datasets, Fashion- MNIST, CIFAR-10, and CIFAR-100, respectively. At the same time, we evaluate our method on neuromorphic N-MNIST, CIFAR10-DVS, and IBM DVS128 Gesture datasets and achieve advanced accuracy in SNN with binary weights. Our network has greater advantages in terms of storage resources and training time.

Florets for Chiplets: Data Flow-aware High-Performance and Energy-efficient Network-on-Interposer for CNN Inference Tasks

Recent advances in 2.5D chiplet platforms provide a new avenue for compact scale-out implementations of emerging compute- and data-intensive applications including machine learning. Network-on-Interposer (NoI) enables integration of multiple chiplets on a 2.5D system. While these manycore platforms can deliver high computational throughput and energy efficiency by running multiple specialized tasks concurrently, conventional NoI architectures have a limited computational throughput due to their inherent multi-hop topologies. In this paper, we propose Floret, a novel NoI architecture based on space-filling curves (SFCs). The Floret architecture leverages suitable task mapping, exploits the data flow pattern, and optimizes the inter-chiplet data exchange to extract high performance for multiple types of convolutional neural network (CNN) inference tasks running concurrently. We demonstrate that the Floret architecture reduces the latency and energy up to 58% and 64%, respectively, compared to state-of-the-art NoI architectures while executing datacenter-scale workloads involving multiple CNN tasks simultaneously. Floret achieves high performance and significant energy savings with much lower fabrication cost by exploiting the data-flow awareness of the CNN inference tasks.

Exploring Trade-Offs in Spiking Neural Networks.

Spiking neural networks (SNNs) have emerged as a promising alternative to traditional deep neural networks for low-power computing. However, the effectiveness of SNNs is not solely determined by their performance but also by their energy consumption, prediction speed, and robustness to noise. The recent method Fast & Deep, along with others, achieves fast and energy-efficient computation by constraining neurons to fire at most once. Known as time-to-first-spike (TTFS), this constraint, however, restricts the capabilities of SNNs in many aspects. In this work, we explore the relationships of performance, energy consumption, speed, and stability when using this constraint. More precisely, we highlight the existence of trade-offs where performance and robustness are gained at the cost of sparsity and prediction latency. To improve these trade-offs, we propose a relaxed version of Fast & Deep that allows for multiple spikes per neuron. Our experiments show that relaxing the spike constraint provides higher performance while also benefiting from faster convergence, similar sparsity, comparable prediction latency, and better robustness to noise compared to TTFS SNNs. By highlighting the limitations of TTFS and demonstrating the advantages of unconstrained SNNs, we provide valuable insight for the development of effective learning strategies for neuromorphic computing.

LoFFT: Low-Voltage FFT Using Lightweight Fault Detection for Energy Efficiency

Operating at reduced voltage is an effective technique for improving the energy efficiency of computing. However, the approach is constrained by its exacerbated sensitivity to Process, Voltage, and Temperature (PVT) variations, which under throughput constraints challenges finding the energy minimizing voltage-frequency operating point. Commonly utilized design approaches for adaptive voltage scaling are based on timing slack measurement or speculation techniques that require adding extra hardware, e.g., Error Detection Sequence (EDS) circuits, that substantially increase the design complexity, and are not applicable for already fabricated designs. In this paper, instead of circuit-level techniques, a low-cost algorithmic error detection method is proposed as the enabler for reduced voltage operation of Fast Fourier Transform (FFT) accelerators.Without requiring neither gate-level nor circuit-level modifications, the method works based on an intrinsic property of the Fourier transform, i.e., Parsevalfs identity. The method is demonstrated on a System-on-Chip (SoC) that integrates a Field-Programmable Gate Array (FPGA) made to operate at reduced voltages. The fault detection capability is profiled using the demonstration test bench, implemented both as software and as hardware. In the experiments, a.43% reduction in power consumption was achieved without sacrificing the throughput and reliability. The overheads of the proposed fault detection approach scale sub-linearly with respect to FFT size and are ≤10% for 1024-point FFT.

Edge–Cloud Collaborative Computation Offloading for Mixed Traffic

Edge computing can avoid long network transmission delay, thus reducing the task response time. However, edge servers cannot respond quickly to massive computing requests due to limited computing power, which may lead to long queuing delays, thus failing to meet low latency requirements of delay-sensitive Internet of Things (IoT) applications. Furthermore, the per-computing-unit energy consumption in edge computing is much higher than that in cloud computing. This article studies the edge–cloud collaborative computing for energy efficiency while meeting the delay requirements of IoT applications in mobile edge computing systems. We formulate the energy efficient computation offloading problem for mixed tasks, including divisible and indivisible tasks. We theoretically analyze the relationship between delay guarantee and energy consumption in edge–cloud collaborative environment. We further analyze the system stability based on Lyapunov stability theory. Then, an energy efficient and delay guaranteed edge–cloud collaborative computation offloading algorithm is proposed to provide delay guarantee for delay-sensitive IoT applications while minimizing the energy consumption of the edge–cloud computing system. Theoretical analysis and experimental results show that, compared with the benchmark algorithms, our algorithm can provide strict delay guarantee for stringent-delay-sensitive IoT applications, and low delay for soft-delay-sensitive IoT applications, while consuming lower energy.

Programmable In-memory Computing Circuit of Fast Hartley Transform

Discrete Hartley transform is a core component of digital signal processing because of its advantages of fast computing speed and less power consumption. Traditional FPGA-based implementation methods have the disadvantage of high latency, which cannot meet the needs of energy-efficient computing in the Internet of Things era. Therefore, A programmable analog memory computing circuit is proposed to accelerate FHT and IFHT calculations for large-scale one-step matrix computation. By adjusting the weight of memristor, different scales of FHT calculation can be achieved. PSPICE simulation results show that the average accuracy of the proposed circuit can reach 99.9%, and the speed can also reach the level of 0.1 μ s. The robustness analysis shows that the circuit can tolerate a certain degree of programming error and resistance tolerance. The designed analog circuit is applied to image compression processing, and the image compression accuracy can reach 99.9%.

HedgeRank: Heterogeneity-Aware, Energy-Efficient Partitioning of Personalized PageRank at the Edge.

Personalized PageRank (PPR) is a widely used graph processing algorithm used to calculate the importance of source nodes in a graph. Generally, PPR is executed by using a high-performance microprocessor of a server, but it needs to be executed on edge devices to guarantee data privacy and network latency. However, since PPR has a variety of computation/memory characteristics that vary depending on the graph datasets, it causes performance/energy inefficiency when it is executed on edge devices with limited hardware resources. In this paper, we propose HedgeRank, a heterogeneity-aware, energy-efficient, partitioning technique of personalized PageRank at the edge. HedgeRank partitions the PPR subprocesses and allocates them to appropriate edge devices by considering their computation capability and energy efficiency. When combining low-power and high-performance edge devices, HedgeRank improves the execution time and energy consumption of PPR execution by up to 26.7% and 15.2% compared to the state-of-the-art PPR technique.

A Bio-inspired Energy Efficient Dynamic Task Scheduling (BEDTS) scheme and classification for virtualization CDC

Cloud Data Centers (CDCs) have evolved into an essential computing infrastructure for businesses. These applications generate a variety of data traffic with varying needs that must be examined and processed on CDCs. Every CDC is made up of multiple servers, virtual infrastructures, and physical connections that manage the internet's informative traffic. CDCs make use of a number of critical technologies, such as virtualization and Service Level Agreements (SLA). Virtualization makes it easier to share cloud computing resources (for example, by separating a powerful Physical Machine (PM) into a series of Virtual Machines (VM)) whose power is comparatively less. Even though virtualization increases the use of PMs by establishing a set of VMs for offering customised services to satisfy the needs of end-users, it also introduces another difficulty to cloud computing: map the VMs to the appropriate PMs. This is referred to as the VM deployment problem, and it is a Nondeterministic Polynomial time problem (NP-problem). CDC task scheduling is appropriate to augment the energy efficiency and resource usage in cloud computing. In the case of real-time tasks in virtualized CDC, the Bio-Inspired Energy Efficient Dynamic Task Scheduling (BEDTS) method is proposed. The Adaptive Elephant Herding Optimization (AEHO) technique is introduced in the BEDTS algorithm for optimal selection of VMs with resource restrictions and jobs. Initially, heterogeneous jobs and VMs are identified using a previous scheduling record. The Bayes classifier and Historical Scheduling Record (HSR), which allow for the identification of both the task type and VM type, serve as the foundation for task categorization. Then, related tasks are combined and then scheduled to make the best use of the host's operational status. When compared to previous approaches, experimental results reveal that BEDTS considerably enhances the scheduling performance on the whole, attains improved CDC resource utilisation, boosts task guarantee ratio, lowers average response time, and decreases the energy usage.

W-AMA: Weight-aware Approximate Multiplication Architecture for neural processing

This paper presents the Weight-aware Approximate Multiplication Architecture (W-AMA) for Deep Neural Networks (DNNs). Considering the Gaussian-like weight distribution, it deploys an accuracy-configurable computing component to improve the computational efficiency. Two techniques for effectively integrating the W-AMA into DNN accelerator are presented: (1) A Cartesian Genetic Programming (CGP) based approximate multiplier is designed and selectable to compute the Least Significant Bit (LSB) for a higher accuracy mode. The Reward–Penalty-Coefficient (RPC) is proposed to achieve the internal-compensation. (2) The Hessian-Aware-Approximation (HAA) method is utilized for hybrid approximate modes cross-layer mapping. Based on the W-AMA, an energy-efficient DNN accelerator is proposed and evaluated on 28 nm technology. It can achieve the energy efficiency of 9.6 TOPS/W, and the computational energy efficiency can be improved by 1.5× compared with the standard units, with an 0.52% accuracy loss on CIFAR-10 using ResNet-18.

Survey of Novel Architectures for Energy Efficient High-Performance Mobile Computing Platforms

There are many real-world applications that require high-performance mobile computing systems for onboard, real-time processing of gathered data due to latency, reliability, security, or other application constraints. Unfortunately, most existing high-performance mobile computing systems require a prohibitively high power consumption in the face of the limited power available from the batteries typically used in these applications. For high-performance mobile computing to be practical, alternative hardware designs are needed to increase the computing performance while minimizing the required power consumption. This article surveys the state-of-the-art in high-efficiency, high-performance onboard mobile computing, focusing on the latest developments. It was found that more research is needed to design high-performance mobile computing systems while minimizing the required power consumption to meet the needs of these applications.