Energy-efficient Computing Research Articles

Leveraging N-1 Queues to Improve the Energy Efficiency of Scalable Computing

The clusters in a blockchain computing system can be constructed to be elastic, thus supporting scalable computing and improving energy efficiency. To form an elastic cluster, the service nodes are dynamically divided into the working nodes and the reserved nodes. Specifically, the working nodes are active to meet the computing requirements of workloads, while the reserved nodes are switched to a low-power state for energy saving. Traditionally, workloads are distributed to working nodes in the mode of N-N service queues. But in this mode, the Quality of Service (QoS) of different working nodes may be diverse, because the requirements are various for the accumulated requests in different working nodes. As a result, the overall system capability is not sufficiently utilized, and the overall system QoS is dragged down. In this paper, we propose an N-1 queueing and on-demand resource provisioning method to process workloads in the mode of N-1 service queues. Different from N-N service queues, N-1 service queues prohibit the accumulation of requests in working nodes. Thereby, once there are idle working nodes, waiting requests can immediately be delivered to them. As a result, all the working nodes are sufficiently utilized, and the overall QoS is improved. Accordingly, after using the N-1 service queues, fewer working nodes are enough to meet the same Service Level Agreement (SLA) on same workloads. In addition, by using a resource demand monitor module, our method dynamically readjusts the number of working nodes to match workload demand. Finally, the energy efficiency of an elastic cluster can be measurably improved, due to that fewer working nodes are powered on while the same SLA can be met.

WOx-Based Synapse Device With Excellent Conductance Uniformity for Hardware Neural Networks

Hardware neural networks (HNNs) which use synapse device (SD) arrays show promise as an approach to energy efficient parallel computation of massive vector-matrix multiplication. To maximize the inference accuracy of application-specific HNNs, we propose a highly reliable 2-terminal SD with fixed resistance based on WOx films. First, we investigate the device requirements of an array-based HNN through MATLAB and SPICE simulations taking into account the parasitic resistance effects in the array. On top of that, to fabricate the SD we utilize the intrinsic properties of the WOx film, which exhibits substantial changes in conductivity from 10−8 to 104 Ω−1cm−1 by varying the oxygen vacancy concentration. After the process optimization of oxide stoichiometry and electrode materials, we can form nanoscale WO×-based SDs with excellent conductance uniformity and I-V linearity. Our results show that inference accuracy is significantly improved by using WOx-based SD arrays even in advanced node scaling. Through experimental hardware implementation, 16 × 16 pixel images are correctly classified and we show the potential of WOx-based SD for future large-scale HNN applications.

Energy Efficient Communication and Computation Resource Slicing for eMBB and URLLC Coexistence in 5G and Beyond

Multi-access edge computing (MEC) enables mobile users to offload their computation tasks to the server located at the edge of the cellular network. Thereby, MEC prolongs the battery lifespan of mobile devices and significantly enhances their computation capacities. However, a significant challenge is to offload the computation tasks to the MEC server in an energy-efficient manner. Meanwhile, in the fifth-generation (5G) networks, mobile users with different service requirements classified as enhanced mobile broadband (eMBB) and ultra-reliable low-latency communications (URLLC) users will coexist in the current cellular network. Therefore, it is important to appropriately multiplex these users in the cellular network. In this work, we address the issues of these two promising technologies together. Firstly, we formulate an energy-efficient task offloading, and scheduling of eMBB and URLLC users as a mixed-integer non-linear problem. Then, we decompose the problem into multiple sub-problems in order to transform into convex form and alternately solve them until converging to the desired solutions by using the block coordinate descent (BCD) algorithm. Finally, we demonstrate numerical results to prove the superior effectiveness in the performance of our proposed algorithm over classical existing schemes.

Long-range temporal correlations in scale-free neuromorphic networks.

Biological neuronal networks are the computing engines of the mammalian brain. These networks exhibit structural characteristics such as hierarchical architectures, small-world attributes, and scale-free topologies, providing the basis for the emergence of rich temporal characteristics such as scale-free dynamics and long-range temporal correlations. Devices that have both the topological and the temporal features of a neuronal network would be a significant step toward constructing a neuromorphic system that can emulate the computational ability and energy efficiency of the human brain. Here we use numerical simulations to show that percolating networks of nanoparticles exhibit structural properties that are reminiscent of biological neuronal networks, and then show experimentally that stimulation of percolating networks by an external voltage stimulus produces temporal dynamics that are self-similar, follow power-law scaling, and exhibit long-range temporal correlations. These results are expected to have important implications for the development of neuromorphic devices, especially for those based on the concept of reservoir computing.

Partial Offloading in Energy Harvested Mobile Edge Computing: A Direct Search Approach

In the next generation wireless communication paradigm, the number of devices are expected to increase exponentially after the concept of Internet of Things (IoT). These devices are power constrained, with limited processing capability. Therefore, in order to get the maximum advantage from these low power IoT sensing devices, it is of utmost need to empower them. Similarly, the devices are not able to process the computationally intensive applications. In this work, Wireless Power Mobile Edge Cloud (WPMEC) is considered, which is an integration of Wireless Power Transfer (WPT) and Mobile Edge Cloud (MEC) to address low power devices' battery and computational capabilities. The WPMEC is charging the devices in the first phase using the WPT and in the second phase, the devices are offloading their computational intensive data to the MEC. Partial offloading scheme is first time introduced and analyzed with WPMEC. Performance of proposed solution is evaluated in terms of overall network computational energy efficiency. Extensive simulations have been carried out to validate the proposed solution. It is shown that the proposed partial offloading scheme with WPMEC outperforms the binary and local computational schemes.

Near-Threshold L1 Data Cache for Yield Management Under Process Variations

Near-threshold computing (NTC) has recently emerged and been considered as a strong candidate for future energy-efficient computing. However, adverse impacts from process variation such as delay and power fluctuations within die as well as across dies are much more severe than the super-threshold regime. In particular, static random access memory (SRAM)-based components (e.g., cache memories) are easily affected by process variation in NTC, resulting in large delay fluctuations. It incurs a huge loss in the maximum clock frequencies of processors, which eventually leads to huge yield losses. In this paper, we first analyze L1 data cache yield in NTC and reveal an inefficiency of frequency binning for yield improvement in NTC. We then introduce a variable latency L1 data cache for NTC to obtain a sufficient yield. By allowing the higher cache access cycles, we can improve cache yield with only a little performance overhead. Moreover, we propose an adaptive line migration technique which improves performance and energy efficiency of variable latency caches. The cache line which is expected to be frequently accessed in the near future is dynamically migrated to the fastest way in a cache set. According to our evaluation, our cache architecture greatly improves cache yield with only a little performance, energy, and area overhead.

Advanced Energy-Efficient Computation Offloading Using Deep Reinforcement Learning in MTC Edge Computing

Mobile edge computing (MEC) supports the internet of things (IoT) by leveraging computation offloading. It minimizes the delay and consequently reduces the energy consumption of the IoT devices. However, the consideration of static communication mode in most of the recent work, despite varying network dynamics and resource diversity, is the main limitation. An energy-efficient computation offloading method using deep reinforcement learning (DRL) is proposed. Both delay-tolerant and non-delay tolerant scenarios are considered using capillary machine type communication (MTC). Depending upon the type of service, an intelligent MTC edge server using DRL decides either process the incoming request at the MTC edge server or sends it to the cloud server. To control communication, we draft a markov decision problem (MDP). This minimizes the long-term power consumption of the system. The formulation of the optimization problem is considered under the constraint of computing power resources and delays. Simulation results delineate the significant performance gain of 12% in computation offloading through the proposed DRL approach. The effectiveness and superiority of the proposed model are compared with other baselines and are demonstrated numerically.

High Performance Energy Efficient Computation Elements of Processing Unit

in our manuscript, various circuits for arithmetic summation are compared. Cadence 90nm technology and Quartus II EP2C20F484C7 are used for implementation of design. Logic gate-based adders, PFCA, TG and HSD technique-based adders characteristics are analyzed. Y finding is PFCA with 10T transistor performs slightly efficient compare to its counterpart. Exclusive OR-NOR design is optimum for least delay Adders for high performance energy efficient processing unit.

Energy-Efficient Computation Offloading and Transmit Power Allocation Scheme for Mobile Edge Computing

Mobile edge computing (MEC) is considered a promising technique that prolongs battery life and enhances the computation capacity of mobile devices (MDs) by offloading computation-intensive tasks to the resource-rich cloud located at the edges of mobile networks. In this study, the problem of energy-efficient computation offloading with guaranteed performance in multiuser MEC systems was investigated. Given that MDs typically seek lower energy consumption and improve the performance of computing tasks, we provide an energy-efficient computation offloading and transmit power allocation scheme that reduces energy consumption and completion time. We formulate the energy efficiency cost minimization problem, which satisfies the completion time deadline constraint of MDs in an MEC system. In addition, the corresponding Karush–Kuhn–Tucker conditions are applied to solve the optimization problem, and a new algorithm comprising the computation offloading policy and transmission power allocation is presented. Numerical results demonstrate that our proposed scheme, with the optimal computation offloading policy and adapted transmission power for MDs, outperforms local computing and full offloading methods in terms of energy consumption and completion delay. Consequently, our proposed system could help overcome the restrictions on computation resources and battery life of mobile devices to meet the requirements of new applications.

Energy Efficiency Analysis Between Green Computing and Cloud Computing

Usually cloud computing is based under effective data computing but green cloud computing focus on energy efficiency of device and computing mainly based on computing architecture. Here cloud computing is also known as green computing due its better effective energy. The purpose of green computing is to decrease the usage of harmful resources, maximizing energy efficiency throughout the living span of the good and also to promote the recyclability or bio degradability of useless goods plus misuse materials of the factory. In order to simulate the hardware by utilizing software, green computing plays a major role for various technologies like virtualization, green data center, cloud and grid computing and power optimization. Here computer resources are effectively utilized by replacing the data center standalone server system by artificial server so as to run the software by less number for large computers called as virtualized. Finally this paper is fulfilled by the advancement of recognized energy efficient computing

Energy-Efficient Convolutional Neural Network Based on Cellular Neural Network Using Beyond-CMOS Technologies

In this article, we perform a uniform benchmarking for the convolutional neural network (CoNN) based on the cellular neural network (CeNN) using a variety of beyond-CMOS technologies. Representative charge-based and spintronic device technologies are implemented to enable energy-efficient CeNN related computations. To alleviate the delay and energy overheads of the fully connected layer, a hybrid spintronic CeNN-based CoNN system is proposed. It is shown that low-power FETs and spintronic devices are promising candidates to implement energy-efficient CoNNs based on CeNNs. Specifically, more than $10\times $ improvement in energy-delay product (EDP) is demonstrated for the systems using spin diffusion-based devices and tunneling FETs compared to their conventional CMOS counterparts.

Synaptic Transistor Capable of Accelerated Learning Induced by Temperature-Facilitated Modulation of Synaptic Plasticity.

Neuromorphic computation, which emulates the signal process of the human brain, is considered to be a feasible way for future computation. Realization of dynamic modulation of synaptic plasticity and accelerated learning, which could improve the processing capacity and learning ability of artificial synaptic devices, is considered to further improve energy efficiency of neuromorphic computation. Nevertheless, realization of dynamic regulation of synaptic weight without an external regular terminal and the method that could endow artificial synaptic devices with the ability to modulate learning speed have rarely been reported. Furthermore, finding suitable materials to fully mimic the response of photoelectric stimulation is still challenging for photoelectric synapses. Here, a floating gate synaptic transistor based on an L-type ligand-modified all-inorganic CsPbBr3 perovskite quantum dots is demonstrated. This work provides first clear experimental evidence that the synaptic plasticity can be dynamically regulated by changing the waveforms of action potential and the environment temperature and both of these parameters originate from and are crucial in higher organisms. Moreover, benefiting from the excellent photoelectric properties and stability of quantum dots, a temperature-facilitated learning process is illustrated by the classical conditioning experiment with and without illumination, and the mechanism of synaptic plasticity is also demonstrated. This work offers a feasible way to realize dynamic modulation of synaptic weight and accelerating the learning process of artificial synapses, which showed great potential in the reduction of energy consumption and improvement of efficiency of future neuromorphic computing.

Software Architecture for Mobile Cloud Computing Systems

Mobile cloud computing (MCC) has recently emerged as a state-of-the-art technology for mobile systems. MCC enables portable and context-aware computation via mobile devices by exploiting virtually unlimited hardware and software resources offered by cloud computing servers. Software architecture helps to abstract the complexities of system design, development, and evolution phases to implement MCC systems effectively and efficiently. This paper aims to identify, taxonomically classify, and systematically map the state of the art on architecting MCC-based software. We have used an evidence-based software engineering (EBSE) approach to conduct a systematic mapping study (SMS) based on 121 qualitatively selected research studies published from 2006 to 2019. The results of the SMS highlight that architectural solutions for MCC systems are mainly focused on supporting (i) software as a service for mobile computing, (ii) off-loading mobile device data to cloud-servers, (iii) internet of things, edge, and fog computing along with various aspects like (iv) security and privacy of mobile device data. The emerging research focuses on the existing and futuristic challenges that relate to MCC-based internet of things (IoTs), mobile-cloud edge systems, along with green and energy-efficient computing. The results of the SMS facilitate knowledge transfer that could benefit researchers and practitioners to understand the role of software architecture to develop the next generation of mobile-cloud systems to support internet-driven computing.

Joint Supercomputer Center of the Russian Academy of Sciences: Present and Future

Joint Supercomputer Center of the Russian Academy of Sciences (JSCC RAS) is the leading supercomputer center for the Russian Academy of Sciences. JSCC RAS uses new technology which is particularly based on native solutions that provide ultra-high dense layout of nodes in the computational field and energy efficiency. JSCC RAS offers users the latest architecture of computing nodes and communications infrastructure. The center has advanced energy-efficient “hot” and “cold” water-cooling systems and a wide range of engineering equipment, a system for monitoring and managing computational resources serving a distributed network of scientific supercomputer centers, a domestic system for scheduling and managing jobs, software development and maintenance tools, application packages for high-performance computing. The paper presents the analysis of the current state of JSCC RAS, and a review of its development plans in the main scientific and practical directions.

Monolithic 3-D Integration

The demands of future applications in computing (from self-driving cars to bioinformatics) overwhelm the projected capabilities of current electronic systems. The need to process unprecedented amounts of loosely structured data is driving the push for ultradense and fine-grained integration of traditionally off-chip components (e.g., sensors, memories) with energy-efficient computation units—all within a single chip. Monolithic 3-D integration is a leading approach for building such future systems, as it naturally enables ultradense connectivity between various heterogeneous technologies inside a single chip. This article discusses exciting recent progress toward realizing monolithic 3-D systems and elucidates key benefits that these new systems offer. Monolithic 3-D integration promises to enable the next wave of gains in performance (both energy and speed) for coming generations of applications as well as provides the means for developing rich additional functionalities such as sensing-immersed-in-computation that lie beyond the scope of traditional computing today.

SAADI-EC: A Quality-Configurable Approximate Divider for Energy Efficiency

Energy efficiency is one of the most crucial constraints that dictate performance, lifetime, form factor, and cost in modern computing system design. However, the energy efficiency improvement driven by semiconductor technology scaling is coming to an end with the prediction of the end of Moore’s law in the near future. Approximate computing is a new paradigm to accomplish energy-efficient computing in this twilight of Moore’s law by relaxing exactness requirement of computation results for intrinsically error-resilient applications, such as some machine learning and signal processing. In this paper, we propose an approximate binary divider design that features dynamic configurability of accuracy and energy consumption. Conventional approximate binary dividers lack runtime energy-quality scalability, which is the key to maximizing energy efficiency while meeting the dynamically varying accuracy requirements of the application. Our divider, named Scalable Accuracy Approximate Divider with Error Compensation (SAADI-EC), supports dynamic energy-quality scalability by the incremental approximation of the reciprocal of the divisor using Taylor series expansion. As a result, the speed and energy efficiency of division can be dynamically traded for accuracy by controlling the number of iterations for the approximation. In addition, SAADI-EC corrects the approximation error using simple, yet effective error compensation hardware to greatly improve the accuracy compared to the base implementation, SAADI. For the 8-bit approximation of 32-bit/16-bit division, the average accuracy of SAADI-EC can be adjusted from 94.2% to 99.6% by varying latency and energy $7\times $ . In terms of $\text {energy}\times \text {delay}$ cost, our design costs up to 87% less than other approximate binary dividers for the same accuracy level. We evaluate the accuracy and energy consumption of SAADI-EC for various design parameters and demonstrate its efficacy for low-power signal processing applications including ${k}$ -means color quantization, JPEG image compression, and image division for video sequences.

A Proof-of-Concept 70 nA ECG Processor for Real-Time R-Wave and NN50 Detection

Unobtrusive health monitoring applications necessitate accurate, real-time, and energy-efficient computation of health-related parameters. Two important parameters for cardiovascular and cardiac autonomic health assessment are heart rate (HR) and heart rate variability (HRV). In this paper, an energy-efficient mixed-signal processor ASIC for real-time monitoring of HR and NN50, a well-established HRV score for parasympathetic activity assessment, is presented. The proposed ASIC, designed in a 0.5 μm CMOS technology, detects R-waves of ECG signals and compares successive R-R intervals to identify the NN50 events in real-time. Post-layout simulation results using ECG signals of four recordings from the MIT-BIH arrhythmia database are compared with DSP calculations on MATLAB. Based on simulation results, the processor detects R-waves with an average accuracy of 99.1%, and NN50 events with average sensitivity and positive predictive values of 94.7% and 96.9%, respectively. The processor consumes 70 nA when supplied by ±1.6 V.

Energy Efficient Cooperative Computation Algorithm in Energy Harvesting Internet of Things

The limited battery capacity of Internet of Things (IoT) devices is a major deployment barrier for IoT-based computing systems. In this paper, we propose an energy efficient cooperative computation algorithm (EE-CCA). In an EE-CCA, a pair of IoT devices decide whether to offload some parts of the task to the opponent by considering their energy levels and the task deadline. To minimize the energy outage probability while completing most of tasks before their deadlines, we formulate a constraint Markov decision process (CMDP) problem and the optimal offloading strategy is obtained by linear programming (LP). Meanwhile, an optimization problem of finding pairs of IoT devices (i.e., IoT device pairing problem) is formulated under the optimal offloading strategy. Evaluation results demonstrate that the EE-CCA can reduce the energy outage probability up to 78 % compared with the random offloading scheme while completing tasks before their deadlines with high probability.

PIMBALL

Neural networks span a wide range of applications of industrial and commercial significance. Binary neural networks (BNN) are particularly effective in trading accuracy for performance, energy efficiency, or hardware/software complexity. Here, we introduce a spintronic, re-configurable in-memory BNN accelerator, PIMBALL: P rocessing I n M emory B NN A cce L(L) erator, which allows for massively parallel and energy efficient computation. PIMBALL is capable of being used as a standard spintronic memory (STT-MRAM) array and a computational substrate simultaneously. We evaluate PIMBALL using multiple image classifiers and a genomics kernel. Our simulation results show that PIMBALL is more energy efficient than alternative CPU-, GPU-, and FPGA-based implementations while delivering higher throughput.

SWARAM

Treatment of patients using high-quality precision medicine requires a thorough understanding of the genetic composition of a patient. Ideally, the identification of unique variations in an individual’s genome is needed for specifying the necessary treatment. Variant calling workflow is a pipeline of tools, integrating state of the art software systems aimed at alignment, sorting and variant calling for the whole genome sequencing (WGS) data. This pipeline is utilized for identifying unique variations in an individual’s genome (compared to a reference genome). Currently, such a workflow is implemented on high-performance computers (with additional GPUs or FPGAs) or in cloud computers. Such systems are large, have a high cost, and rely on the internet for genome data transfer which makes the system unusable in remote locations unequipped with internet connectivity. It further raises privacy concerns due to processing being carried out in a different facility. To overcome such limitations, in this paper, for the first time, we present a cost-efficient, offline, scalable, portable, and energy-efficient computing system named SWARAM for variant calling workflow processing. The system uses novel architecture and algorithms to match against partial reference genomes to exploit smaller memory sizes which are typically available in tiny processing systems. Extensive tests on a standard benchmark data-set (NA12878 Illumina platinum genome) confirm that the time consumed for the data transfer and completing variant calling workflow on SWARAM was competitive to that of a 32-core Intel Xeon server with similar accuracy, but costs less than a fifth, and consumes less than 40% of the energy of the server system. The original scripts and code we developed for executing the variant calling workflow on SWARAM are available in the associated Github repository https://github.com/Rammohanty/swaram.