Energy-efficient Computing Research Articles

High-Density Reconfigurable Synaptic Transistors Targeting a Minimalist Neural Network.

Enormous synaptic devices are required to build a parallel, precise, and efficient neural computing system. To further improve the energy efficiency of neuromorphic computing, a single high-density synaptic (HDS) device with multiple nonvolatile synaptic states is suggested to reduce the number of synaptic devices in the neural network, although such a powerful synaptic device is rarely demonstrated. Here, a photoisomerism material, namely, diarylethene, whose energy level varies with the wavelength of illumination is first introduced to construct a powerful HDS device. The multiple synaptic states of the HDS device are intrinsically converted under UV-vis regulation and remain nonvolatile after the removal of illumination. More importantly, the conversion is reconfigurable and reversible under different light conditions, and the synaptic characteristics are comprehensively mimicked in each state. Finally, compared with a two-layer multilayer perceptron (MLP) architecture based on static synaptic devices, the HDS device-based architecture reduces the device number by 16 times to achieve a minimalist neural computing structure. The invention of the HDS device opens up a revolutionary paradigm for the establishment of a brain-like network.

Метод дифференциального пространственно-временного блокового кодирования для применения в системах подвижной радиосвязи с использованием технологии MIMO.

In radio communication systems, when implementing coherent types of reception, it is assumed that the receiver knows information about the state of the communication channel, which is achieved by introducing signal redundancy (pilot signals). The frequency of sending pilot signals depends on factors that change the state of the communication channel, one of which is the high speed of movement of mobile stations. The use of pilot signals not only hinders the efficient use of the radio frequency resource, but also, in the case of fast fading, does not allow the channel to be estimated and tracked with the required accuracy. These disadvantages can be eliminated by using the differential transmission method, for the implementation of which there is no need to know information about the state of the channel. The application of the principles of differential transmission to space-time coding does not find sufficiently effective solutions that combine low computational complexity and energy efficiency of differential coding methods.

Deep-Green: A Dispersed Energy-Efficiency Computing Paradigm for Green Industrial IoT

The rapid development of the Industrial Internet of Things (IIoT) has led to the explosive growth of industrial control data. Cloud computing-based industrial control models cause vast energy consumption. Most existing solutions try to reduce the overall energy consumption by optimizing task scheduling and disregard how to reduce the load of computing and data transmission. On the other hand, due to the rigid architecture and limited capability of the edge computing platform, solutions based on edge computing urgently need to be deeply optimized in terms of data processing and energy efficiency. This paper proposes Deep-Green, which is a dispersed energy-efficient computing paradigm for the Industrial Internet of Things. The core idea of Deep-Green is to realize the joint optimization of computing and network resources by merging data transmission and data processing. Deep-Green provides a novel method of constructing an IIoT edge layer based on a dispersed computing platform. By using an energy-efficiency task scheduling algorithm, container service technology, and programmable protocol stack, the data processing service is dispatched from the cloud side to the on-site controller. Therefore, the data from manufacturing equipment can be processed while they are forwarded by the on-site industrial controller. The results of experiments show that Deep-Green can not only effectively reduce the computing load and communication overhead of the cloud-side server, but also simplify the network topology and the number of devices at the edge layer of the IIoT.

Synaptic Behavior and Conduction Mechanisms in Core-Shell Nanowires for Neuromorphic Hardware Applications

To tackle the ever-increasing demand for faster computation time and energy efficiency, analog neuromorphic architectures have been proposed in place of current artificial neural networks (ANNs) to emulate the computational abilities of the brain. Non-volatile, two terminal devices like memristors have been proven as viable candidates as an artificial synapse in these architectures. Presently, these devices are fabricated as crossbar, thin-film or nanowires. Nanowire-based architectures can play an important role in enhancing sparsity and randomness of a network, particularly when built using core-shell structures. We have previously shown that, depending on the forming process, a Pt core and HfO2 shell nanowire with a Ti top electrode can display eightwise (8W) or counter eightwise (C8W) bipolar resistive switching (BRS) at low potential ranges (±1 V). We will show that the symmetry of the core-shell nanowires combined with the 8W and C8W switching observed, are indicative of anti-serial memristor arrangement. Moreover, this configuration allows for the individual nanowires to exhibit complementary resistive switching (CRS) at higher potentials (±2 V). We will also show the current conduction mechanisms of this system, where thermionic emission dominates in the low resistance state while ohmic conduction dominates in the high resistance state, when the device is operated in BRS mode; and hopping conduction dominates in state 0 while space-charge-limited conduction dominates in state 1 when, the device is operated in CRS mode. When in BRS mode, the LRS and HRS states are stable for at least 1000 cycles and retain memory for 104 s. Finally, when testing for synaptic plasticity via long-term potentiation and depression (LTP and LTD), non-linear weight update behavior was observed. The effect of voltage pulse schemes on the synaptic response will be discussed in detail.

Neuromorphic photonics: 2D or not 2D?

The computing industry is rapidly moving from a programming to a learning area, with the reign of the von Neumann architecture starting to fade, after many years of dominance. The new computing paradigms of non-von Neumann architectures have started leading to the development of emerging artificial neural network (ANN)-based analog electronic artificial intelligence (AI) chipsets with remarkable energy efficiency. However, the size and energy advantages of electronic processing elements are naturally counteracted by the speed and power limits of the electronic interconnects inside the circuits due to resistor-capacitor (RC) parasitic effects. Neuromorphic photonics has come forward as a new research field, which aims to transfer the well-known high-bandwidth and low-energy interconnect credentials of photonic circuitry in the area of neuromorphic platforms. The high potential of neuromorphic photonics and their well-established promise for fJ/Multiply-ACcumulate energy efficiencies at orders of magnitudes higher neuron densities require a number of breakthroughs along the entire technology stack, being confronted with a major advancement in the selection of the best-in-class photonic material platforms for weighting and activation functions and their transformation into co-integrated photonic computational engines. With this paper, we analyze the current status in neuromorphic computing and in available photonic integrated technologies and propose a novel three-dimensional computational unit which, with its compactness, ultrahigh efficiency, and lossless interconnectivity, is foreseen to allow scalable computation AI chipsets that outperform electronics in computational speed and energy efficiency to shape the future of neuromorphic computing.

On the origin of the controversial electrostatic field effect in superconductors

Superconducting quantum devices offer numerous applications, from electrical metrology and magnetic sensing to energy-efficient high-end computing and advanced quantum information processing. The key elements of quantum circuits are (single and double) Josephson junctions controllable either by electric current or magnetic field. The voltage control, commonly used in semiconductor-based devices via the electrostatic field effect, would be far more versatile and practical. Hence, the field effect recently reported in superconducting devices may revolutionise the whole field of superconductor electronics provided it is confirmed. Here we show that the suppression of the critical current attributed to the field effect, can be explained by quasiparticle excitations in the constriction of superconducting devices. Our results demonstrate that a miniscule leakage current between the gate and the constriction of devices perfectly follows the Fowler-Nordheim model of electron field emission from a metal electrode and injects quasiparticles with energies sufficient to weaken or even suppress superconductivity.

Analysis on energy efficient green cloud computing

Cloud computing offers subscription based storage and resources. Cloud computing provides various services to cloud users. Increased use of information and communication technologies (ICT) has led to increase energy cost as well also increased emission of greenhouse gases like CO2. Since energy is an important asset, green cloud computing comes into picture. Green cloud computing can be achieved by applying various approaches, which uses lesser power as well as emits less CO2 gas, which is hazardous to environment. Energy efficient technologies results in decreased overall energy consumption. There is a need of data centre in almost every field like web applications and businesses which results in producing huge amount of CO2 in environment. To make data centres environmental friendly we need energy efficient approaches which will reduce energy consumption and there hazardous effects on environment. Data is being generated at very high speed so the need of data centres will also increase. Increased data centres will then consume more amount of energy. The main objective of these paper is to reviews various approaches applied by researchers to make energy efficient cloud computing.

Robust Computation Offloading in Fog Radio Access Network With Fronthaul Compression

Deployed with computation resources, fog radio access network (F-RAN) provides a promising solution for computation offloading. To take full advantage of two-tier computing in the F-RAN, on one hand, it is inevitable to design, between edge and cloud, an efficient and flexible fronthaul transmission strategy, and fronthaul resource allocation should be jointly optimized with allocation of tasks and other resources. On the other hand, a robust computation provisioning strategy that can avoid failures caused by estimation errors of available computation resources is necessary. In this work, considering the fronthaul compression and the uncertain computation capacity, we design an energy-efficient computation offloading mechanism in the F-RAN. The formulated problem is challenging to solve due to coupled communication and computation resource constraints and binary variables for task placement. We show that the problem can be recast as a convex problem if binary variables are relaxed. On top of this result, we propose an efficient algorithm to find a stationary solution. Through simulation, we demonstrate that the proposed algorithm outperforms the baseline algorithm significantly and converges to the near-optimal point solution. Besides, we compare the F-RAN with single-tier computing systems and show the excellence of the F-RAN in energy conservation for mobile devices.

Towards Sustainable Crossbar Artificial Synapses with Zinc-Tin Oxide

In this article, characterization of fully patterned zinc-tin oxide (ZTO)-based memristive devices with feature sizes as small as 25 µm2 is presented. The devices are patterned via lift-off with a platinum bottom contact and a gold-titanium top contact. An on/off ratio of more than two orders of magnitude is obtained without the need for electroforming processes. Set operation is a current controlled process, whereas the reset is voltage dependent. The temperature dependency of the electrical characteristics reveals a bulk-dominated conduction mechanism for high resistance states. However, the charge transport at low resistance state is consistent with Schottky emission. Synaptic properties such as potentiation and depression cycles, with progressive increases and decreases in the conductance value under 50 successive pulses, are shown. This validates the potential use of ZTO memristive devices for a sustainable and energy-efficient brain-inspired deep neural network computation.

Materials Strategies for Organic Neuromorphic Devices

Neuromorphic computing is becoming increasingly prominent as artificial intelligence (AI) facilitates progressively seamless interaction between humans and machines. The conventional von Neumann architecture and complementary metal-oxide-semiconductor transistor scaling are unable to meet the highly demanding computational density and energy efficiency requirements of AI. Neuromorphic computing aims to address these challenges by using brain-like computing architectures and novel synaptic memories that coallocate information storage and computation, thereby enabling low latency at high energy efficiency and high memory density. Though various emerging memory devices have been extensively studied to emulate the functionality of biological synapses, there is currently no material/device system that encompasses both the needed metrics for high-performance neuromorphic computing and the required biocompatibility for potential body-computer integration. In this review, we aim to equip the reader with general design principles and materials requirements for realizing high-performance organic neuromorphic devices. We use instructive examples from recent literature to discuss each requirement, illustrating the challenges as well as future research opportunities. Though organic devices still face many challenges to become major players in neuromorphic computing, mostly due to their lack of compliance with back-end-of-line processes required for integration with digital logic, we propose that their biocompatibility and mechanical conformability give them an advantage for creating adaptive biointerfaces, brain-machine interfaces, and biology-inspired prosthetics.

CARLA: A Convolution Accelerator With a Reconfigurable and Low-Energy Architecture

Convolutional Neural Networks (CNNs) have proven to be extremely accurate for image recognition, even outperforming human recognition capability. When deployed on battery-powered mobile devices, efficient computer architectures are required to enable fast and energy-efficient computation of costly convolution operations. Despite recent advances in hardware accelerator design for CNNs, two major problems have not yet been addressed effectively, particularly when the convolution layers have highly diverse structures: (1) minimizing energy-hungry off-chip DRAM data movements; (2) maximizing the utilization factor of processing resources to perform convolutions. This work thus proposes an energy-efficient architecture equipped with several optimized dataflows to support the structural diversity of modern CNNs. The proposed approach is evaluated on convolutional layers of VGGNet-16 and ResNet-50. Results show that the architecture achieves a Processing Element (PE) utilization factor of 98% for the majority of 3×3 and 1×1 convolutional layers, while limiting latency to 396.9 ms and 92.7 ms when performing convolutional layers of VGGNet-16 and ResNet-50, respectively. In addition, the proposed architecture benefits from the structured sparsity in ResNet-50 to reduce the latency to 42.5 ms when half of the channels are pruned.

Energy-Efficient Multiaccess Edge Computing for Terrestrial-Satellite Internet of Things

The recent advances in low earth orbit (LEO) satellites enable the satellites to provide task processing capability for remote Internet-of-Things (IoT) mobile devices (IMDs) without proximal multiaccess edge computing (MEC) servers. In this article, by leveraging the LEO satellites, a novel MEC framework for terrestrial-satellite IoT is proposed. With the aid of terrestrial-satellite terminal (TST), the computation offloading from IMDs to LEO satellites is divided into two stages in the ground and space segments. In order to minimize the weighted-sum energy consumption of IMDs, we decompose the formulated problem into two layered subproblems: 1) the lower layer subproblem minimizing the latency of space segment, which is solved by sequential fractional programming with attaining the first-order optimality and 2) the upper layer subproblem that is solved by exploiting the convex structure and applying the Lagrangian dual decomposition method. Based on the solutions to the two layered subproblems, an energy-efficient computation offloading and resource allocation algorithm (E-CORA) is proposed. By simulations, it is shown that: 1) there exists a specific amount of offloading bits, which can minimize the energy consumption of IMDs and the proposed E-CORA outperforms full offloading and local computing only; 2) larger transmit power of the TST helps to save the energy of IMDs; and 3) by increasing the number of visible satellites, the ratio of offloading bits increases while the energy consumption of IMDs can be decreased.

Network and Application Performance Measurement Challenges on Android Devices

Modern mobile systems are optimized for energy-efficient computation and communications, and these optimizations affect the way they use the network, and thus the performance of the applications. Therefore, understanding network and application performance are essential for debugging, improving user experience, and performance comparison. In recent years, several tools have emerged that analyze network performance of mobile applications in situ with the help of the VPN service. However, there is a limited understanding of how these measurement tools and system optimizations affect the network and application performance. This paper first demonstrates that mobile systems employ energy-aware system hardware tuning, affecting network latency and throughput. We next show that the VPN-based tools, such as Lumen, PrivacyGuard, and Video Optimizer, aid in ambiguous network performance measurements and degrade the application performance. Our findings suggest that sound Internet traffic measurement on Android devices requires a good understanding of the device, networks, measurement tools, and applications.

Network Blueprint for Maximizing the Lifetime of Smart Devices in Low Power IoT Networks

In the modern communication and computation era, internet of things (IoT) is developing as the key technology that satisfies the requirements of various applications. Prolonging device lifetime and maintaining network reliability is the evident objective for IoT network. Therefore, the authors come up with the network architecture that integrates node placement technique and routing technique. In the architecture, node placement is implemented by varying the density of nodes, by varying battery level of nodes, and by varying transmission range of nodes. Energy efficient and reliable path computation is addressed by routing technique. Therefore, enhancing the features of routing and node placement technique and integrating them together in network architecture can efficiently prolong the network lifetime. From the results, the authors observed that the proposed network architecture prolongs the network lifetime two times better than the standard model and also outperforms EQSR protocol and maintains the reliable data transfer.

Low-Latency Spiking Neural Networks Using Pre-Charged Membrane Potential and Delayed Evaluation.

Spiking neural networks (SNNs) have attracted many researchers’ interests due to its biological plausibility and event-driven characteristic. In particular, recently, many studies on high-performance SNNs comparable to the conventional analog-valued neural networks (ANNs) have been reported by converting weights trained from ANNs into SNNs. However, unlike ANNs, SNNs have an inherent latency that is required to reach the best performance because of differences in operations of neuron. In SNNs, not only spatial integration but also temporal integration exists, and the information is encoded by spike trains rather than values in ANNs. Therefore, it takes time to achieve a steady-state of the performance in SNNs. The latency is worse in deep networks and required to be reduced for the practical applications. In this work, we propose a pre-charged membrane potential (PCMP) for the latency reduction in SNN. A variety of neural network applications (e.g., classification, autoencoder using MNIST and CIFAR-10 datasets) are trained and converted to SNNs to demonstrate the effect of the proposed approach. The latency of SNNs is successfully reduced without accuracy loss. In addition, we propose a delayed evaluation method (DE), by which the errors during the initial transient are discarded. The error spikes occurring in the initial transient is removed by DE, resulting in the further latency reduction. DE can be used in combination with PCMP for further latency reduction. Finally, we also show the advantages of the proposed methods in improving the number of spikes required to reach a steady-state of the performance in SNNs for energy-efficient computing.

A Dual-Mode In-Memory Computing Unit Using Spin Hall-Assisted MRAM for Data-Intensive Applications

The emerging big data application poses many non-traditional challenges to a conventional computing system. The processing of a large amount of data in a conventional computing system involves frequent data movement between the processor and the memory. As a result, power consumption and latency of the system increases, most commonly known as the von Neumann bottleneck. To address this von Neumann bottleneck, processing in memory is considered one of the most promising solutions for energy-efficient computing in data-intensive applications. Therefore, in this work, we propose an in-memory computing unit based on emerging non-volatile magnetic random access memory (MRAM), which can perform computations directly within the memory. We call the proposed memory unit computational MRAM (C-MRAM). The proposed array works in two modes: 1) memory mode, where it acts as standard memory with the additional advantage of non-volatility, and 2) logic mode, where it performs the computation inside the memory array. To demonstrate the benefits of the proposed C-MRAM array, we realize an approximate adder (Ax-ADD) for energy-constraint applications in which further power saving is achieved by relaxing the demand for computational accuracy. Furthermore, we propose to use the C-MRAM array in hybrid multi-bank architecture, which offers the flexibility of reconfiguring the proposed C-MRAM as a memory array or logic array to meet the requirement of a wide range of applications. The simulation result shows that the proposed array can efficiently perform memory, logic, and arithmetic operation in 2, 4, and 6 ns while consuming 0.2, 0.47, and 0.7 pJ of energy.

Computational EE Fairness in Backscatter-Assisted Wireless Powered MEC Networks

In this letter, we study the computational energy efficiency (EE) fairness in a backscatter-assisted wireless powered mobile edge computing (MEC) network, where multiple edge users (EUs) can offload tasks to the MEC server via passive backscatter communications (BackComs) and active transmissions (ATs) under the guidance of the harvest-then-transfer protocol. Specifically, with the practical non-linear energy harvesting (EH) model and the partial offloading scheme considered at each EU, we propose a max-min computational EE-based resource allocation scheme to ensure the fairness among multiple EUs by jointly optimizing the reflection coefficient, transmit power, local computing frequency and execution time of each EU, as well as EUs' time sharing between BackComs and ATs, and then develop a Dinkelbach-based iterative algorithm to obtain the optimal solutions. We further employ the Lagrange duality method to obtain instrumental insights on the max-min computational EE-based resource allocation scheme. Simulation results verify the superiority of the proposed scheme over benchmark schemes in terms of computational EE fairness.

Energy-efficient event pattern recognition in wireless sensor networks using multilayer spiking neural networks

Motivated by the energy-efficient computation of the brain, an energy-efficient wireless sensor network infrastructure is built for solving the pattern recognition task. In this work, spatiotemporal patterns originate from the wireless sensor nodes that use pulse-based networking schemes like pulse position-coded packet data unit and spiked time-division multiple access. Pulse-based networking schemes use spatiotemporal patterns to encode information rather than using traditional energy-expensive packets. These spatiotemporal patterns are learned through biologically plausible learning rule of Tempotron which is a neuronal binary classifier that uses a gradient-descent supervised learning rule to adjust the weights of synaptic inputs. A single Tempotron-trained spiking neuron is shown to read out information encoded in the spike timings of synaptic inputs. However, due to the simplicity of the single Tempotron classifier, its performance is inherently limited. In this work, we devise the multilayer spiking neuron training rules for event pattern classification in distributed wireless sensor networks. We also show that the proposed architecture improves classification accuracy by a considerable amount as compared to a single Tempotron model’s performance.

Kurbanova. Design of energy-efficient high-speed computer equipment based on cost-effective light transistors

Objective. The article deals with the formation of cost-effective light transistors for creating high-speed energy-efficient computer structures that can solve numerous problems with high speed and accuracy. For this purpose, various types of semiconductor structures are used that can emit and absorb photons for receiving and transmitting digital information.Methods. The use of mirror electrodes allows for repeated re-reflection of the generated photons inside the light transistor to recover all the generated energy into electricity. This increases the energy efficiency of the transistor as a whole and allows implementing computer devices with high efficiency in solving various tasks.Results. Most of the useful energy of the information signal is transferred from one electrode to another, and the movement has a higher speed due to the use of photons, rather than drifting electrons, and this indirectly increases the speed of the light transistor by several orders of magnitude and effectively solves the problem of implementing more powerful and high-speed transistors with greater economic benefits.Conclusion. Prospects for the implementation of high-speed energy-efficient computer structures based on both bipolar transistors and unipolar transistors, as well as thyristors, lasers, and other semiconductor components in light-emitting structures have been developed.

An optical neural chip for implementing complex-valued neural network

Complex-valued neural networks have many advantages over their real-valued counterparts. Conventional digital electronic computing platforms are incapable of executing truly complex-valued representations and operations. In contrast, optical computing platforms that encode information in both phase and magnitude can execute complex arithmetic by optical interference, offering significantly enhanced computational speed and energy efficiency. However, to date, most demonstrations of optical neural networks still only utilize conventional real-valued frameworks that are designed for digital computers, forfeiting many of the advantages of optical computing such as efficient complex-valued operations. In this article, we highlight an optical neural chip (ONC) that implements truly complex-valued neural networks. We benchmark the performance of our complex-valued ONC in four settings: simple Boolean tasks, species classification of an Iris dataset, classifying nonlinear datasets (Circle and Spiral), and handwriting recognition. Strong learning capabilities (i.e., high accuracy, fast convergence and the capability to construct nonlinear decision boundaries) are achieved by our complex-valued ONC compared to its real-valued counterpart.