Energy-efficient Computing Research Articles

Synapse and Tunable Leaky-Integrate Neuron Functions Enabled by Oxide Trapping Dynamics in a Single Logic Transistor

We show that a high-k gated n-MOSFET can embody both the memory plasticity of a synapse and leaky-integration of a neuron, by virtue of the rich temporal dynamics of charge capture/emission by gate-oxide defects. In addition, a tunable leaky-integrate function is demonstrated. The lower limit of energy per input spike is on the order of fJ, which provides room for low-power trigger circuit design and scalability. This work points to the prospect of a gate-engineered logic transistor serving as the universal building block of hardware spiking neural networks, thereby accelerating the realization of compact, energy efficient neuromorphic computers given the relative maturity of the transistor technology.

Photonic and optoelectronic neuromorphic computing

Recent advances in neuromorphic computing have established a computational framework that removes the processor-memory bottleneck evident in traditional von Neumann computing. Moreover, contemporary photonic circuits have addressed the limitations of electrical computational platforms to offer energy-efficient and parallel interconnects independently of the distance. When employed as synaptic interconnects with reconfigurable photonic elements, they can offer an analog platform capable of arbitrary linear matrix operations, including multiply–accumulate operation and convolution at extremely high speed and energy efficiency. Both all-optical and optoelectronic nonlinear transfer functions have been investigated for realizing neurons with photonic signals. A number of research efforts have reported orders of magnitude improvements estimated for computational throughput and energy efficiency. Compared to biological neural systems, achieving high scalability and density is challenging for such photonic neuromorphic systems. Recently developed tensor-train-decomposition methods and three-dimensional photonic integration technologies can potentially address both algorithmic and architectural scalability. This tutorial covers architectures, technologies, learning algorithms, and benchmarking for photonic and optoelectronic neuromorphic computers.

Inverse linear versus exponential scaling of work penalty in finite-time bit reset.

A bit reset is a basic operation in irreversible computing. This costs work and dissipates energy in the computer, creating a limit on speeds and energy efficiency of future irreversible computers. It was recently shown by Zhen etal. [Phys. Rev. Lett. 127, 190602 (2021)0031-900710.1103/PhysRevLett.127.190602] that for a finite-time reset protocol, the additional work on top of the quasistatic protocol can always be minimized by considering a two-level system, and then be lower bounded through a thermodynamical speed limit. An important question is to understand under what protocol parameters, including a bit reset error and maximum energy shift, this penalty decreases exponentially vs inverse linearly in the protocol time. Here we provide several analytical results to address this question, as well as numerical simulations of specific examples of protocols.

Power-based Attacks on Spatial DNN Accelerators

With proliferation of DNN-based applications, the confidentiality of DNN model is an important commercial goal. Spatial accelerators, which parallelize matrix/vector operations, are utilized for enhancing energy efficiency of DNN computation. Recently, model extraction attacks on simple accelerators, either with a single processing element or running a binarized network, were demonstrated using the methodology derived from differential power analysis (DPA) attack on cryptographic devices. This article investigates the vulnerability of realistic spatial accelerators using general, 8-bit, number representation. We investigate two systolic array architectures with weight-stationary dataflow: (1) a 3 × 1 array for a dot-product operation and (2) a 3 × 3 array for matrix-vector multiplication. Both are implemented on the SAKURA-G FPGA board. We show that both architectures are ultimately vulnerable. A conventional DPA succeeds fully on the 1D array, requiring 20K power measurements. However, the 2D array exhibits higher security even with 460K traces. We show that this is because the 2D array intrinsically entails multiple MACs simultaneously dependent on the same input. However, we find that a novel template-based DPA with multiple profiling phases is able to fully break the 2D array with only 40K traces. Corresponding countermeasures need to be investigated for spatial DNN accelerators.

Influence of environmental variables on the energy efficiency of drinking water treatment plants

Evaluating and benchmarking the energy efficiency of drinking water treatment plants (DWTPs) is essential to improve the environmental and economic performance of these facilities. However, robust and reliable methods should be used to compute energy efficiency scores to avoid biased conclusions. In this study, the stochastic non-parametric envelopment of data (StoNED) method was employed to assess the energy efficiency of a sample of 146 DWTPs. This methodological approach also allowed us to explore the influence of several environmental variables on the energy performance of DWTPs. The average energy efficiency score of the facilities evaluated was 0.461. It means that they could save 54% of the current energy consumption. 42% of the DWTPs evaluated presented an average energy efficiency score varied between 0.41 and 0.61. None of the 146 water treatment facilities was identified as fully energy efficient which evidences that all DWTPs could save energy. The source of raw water, the age of the DWTP and the main technology used to treat raw water were factors that statistically affected the energy efficiency of DWTPs. It was also estimated that a 1% increase in the removal of total dissolved solids and sulfates result in an increase in energy consumption by 0.340 and 0.409%, respectively, ceteris paribus. The information and conclusions of this study are of great interest for water managers and regulators to improve the operation of DWTPs and plan the design of new facilities.

Optimal Design and Orchestration of Mobile Edge Computing With Energy Awareness

The wireless networks beyond the fifth generation (5G) are envisioned to be the platform that will support a vast amount of diversified data-driven applications with stringent requirements in terms of computational accuracy, delay, and energy efficiency. The fulfillment of this objective can be achieved by the convergence of communication and computing networks, enabling the exploitation of edge computing resources and the joint orchestration of the corresponding resources. Mobile edge computing (MEC), which refers to the use of edge serves for offloading tasks from mobile devices, is a particularly promising approach to provide the required computational performance for emerging internet-of-things applications, such as the smart grids, smart industry, healthcare, and smart farming. In this work, we propose the use of an advanced multiple access technique and its joint design with adaptive task offloading, in order to reduce delay and energy consumption. More specifically, the use of generalized hybrid orthogonal/non-orthogonal multiple access (OMA/NOMA) for MEC is introduced, which is theoretically superior to other alternatives from the existing literature. In more detail, the proposed scheme is based on the joint utilization of dynamic user scheduling among OMA/NOMA phases and variable decoding order during the successive interference cancellation in NOMA phase. Also, the system’s orchestration is optimized for both full and partial task offloading. Specifically, in full offloading scenario, the user scheduling, time allocation, and power control are jointly optimized. Regarding partial offloading, the computational resources, i.e., the clock speed of the local processors and the number of offloaded bits, are jointly optimized with the communication resources, taking into account the constraint of the energy that is consumed for both local processing and task offloading, which is particularly challenging due to the non-convex nature of the corresponding optimization problem. All optimization problems are efficiently solved by either using closed-form solutions that provide useful insights or low-complexity algorithms. Finally, simulation results demonstrate the effectiveness of the proposed techniques and provide useful insights on the system’s performance, in terms of average delay and energy consumption.

Representing stimulus information in an energy metabolism pathway

We explored a computational model of astrocytic energy metabolism and demonstrated the theoretical plausibility that this type of pathway might be capable of coding information about stimuli in addition to its known functions in cellular energy and carbon budgets. Simulation results indicate that glycogenolytic glycolysis triggered by activation of adrenergic receptors can capture the intensity and duration features of a neuromodulator waveform and can respond in a dose-dependent manner, including non-linear state changes that are analogous to action potentials. We show how this metabolic pathway can translate information about external stimuli to production profiles of energy-carrying molecules such as lactate with a precision beyond simple signal transduction or non-linear amplification. The results suggest the operation of a metabolic state-machine from the spatially discontiguous yet interdependent metabolite elements. Such metabolic pathways might be well-positioned to code an additional level of salient information about a cell’s environmental demands to impact its function. Our hypothesis has implications for the computational power and energy efficiency of the brain.

A review on SRAM-based computing in-memory: Circuits, functions, and applications

Artificial intelligence (AI) processes data-centric applications with minimal effort. However, it poses new challenges to system design in terms of computational speed and energy efficiency. The traditional von Neumann architecture cannot meet the requirements of heavily data-centric applications due to the separation of computation and storage. The emergence of computing in-memory (CIM) is significant in circumventing the von Neumann bottleneck. A commercialized memory architecture, static random-access memory (SRAM), is fast and robust, consumes less power, and is compatible with state-of-the-art technology. This study investigates the research progress of SRAM-based CIM technology in three levels: circuit, function, and application. It also outlines the problems, challenges, and prospects of SRAM-based CIM macros.

Energy-efficient distributed password hash computation on heterogeneous embedded system

This paper presents the improved version of our cool Cracker cluster (cCc), a heterogeneous distributed system for parallel and energy-efficient bcrypt password hash computation. The cluster consists of up to 8 computational units (nodes) with different performances measured in bcrypt hash computations per second [H/s]. In the cluster, nodes are low-power heterogeneous embedded systems with programmable logic containing specialized hash computation accelerators. In the experiments, we used a combination of Xilinx Zynq-series SoC boards and ZTEX 1.15y board which was initially used as a bitcoin miner. Zynq based nodes use the improved version of our custom bcrypt accelerator, which executes the most costly parts of the bcrypt hash computation in programmable logic. The cluster was formed around the famous open-source password cracking software package John the Ripper (abbr. JtR). On the communication layer, we used Message Passing Interface (MPI)library with a standard Ethernet network connecting the nodes. To mitigate the different performances among the cluster nodes and to balance the load, we developed and implemented password candidate distribution scheme based on the passwords' probability distribution, i.e. the order of appearance in the dictionary. We tested individual nodes and the cluster as a whole, trying different combinations of nodes and evaluating our distribution scheme for password candidates. We also compared our cluster with various GPU implementations in terms of performance, energy-efficiency, and price-efficiency. We show that our solution outperforms other platforms such as high-end GPUs, by a factor of at least 3 in terms of energy-efficiency and thus producing less overall cost of password attack than other platforms. In terms of the total operational costs, our cluster pays off after 4500 cracked passwords for a bcrypt hash with cost parameter 12, which makes it more appealing for real-world password-based system attacks. We also demonstrate the scalability of our cCc cluster.

Flexible synaptic floating gate devices with dual electrical modulation based on ambipolar black phosphorus

SummaryTwo-dimensional van der Waals materials offer various possibilities for synaptic devices, matching the requirements of intelligent and energy-efficient computation. However, very few studies on robust flexible synaptic transistors have been reported, which hold great potential for soft robotics and wearable applications. Here a floating gate synaptic device based on ambipolar black phosphorus (BP) on a flexible substrate has been demonstrated with two working modes. The three-terminal mode, where the carriers are injected into the floating gate, shows a nonvolatile memory effect, whereas the two-terminal mode shows a quasi-nonvolatile memory effect. Remarkably, the synaptic device working on the three-terminal mode shows an excellent performance in the energy-efficient computation of sub-fJ/spike with a fast gate voltage response down to ∼10 ns. Furthermore, the flexible synaptic device exhibits good endurance under 5,000 bending cycles with a strain of ∼0.63%, suggesting great potential in flexible neuromorphic applications with low energy consumption.

A Biomimetic Tunnel FET-Based Spiking Neuron for Energy-Efficient Neuromorphic Computing With Reduced Hardware Cost

A Biomimetic Tunnel FET-Based Spiking Neuron for Energy-Efficient Neuromorphic Computing With Reduced Hardware Cost

Energy Efficient Computing Systems: Architectures, Abstractions and Modeling to Techniques and Standards

Computing systems have undergone a tremendous change in the last few decades with several inflexion points. While Moore’s law guided the semiconductor industry to cram more and more transistors and logic into the same volume, the limits of instruction-level parallelism (ILP) and the end of Dennard’s scaling drove the industry towards multi-core chips. More recently, we have entered the era of domain-specific architectures (DSA) and chips for new workloads like artificial intelligence (AI) and machine learning (ML). These trends continue, arguably with other limits, along with challenges imposed by tighter integration, extreme form factors and increasingly diverse workloads, making systems more complex to architect, design, implement and optimize from an energy efficiency perspective. Energy efficiency has now become a first order design parameter and constraint across the entire spectrum of computing devices. Many research surveys have gone into different aspects of energy efficiency techniques implemented in hardware and microarchitecture across devices, servers, HPC/cloud, data center systems along with improved software, algorithms, frameworks, and modeling energy/thermals. Somewhat in parallel, the semiconductor industry has developed techniques and standards around specification, modeling/simulation, benchmarking and verification of complex chips; these areas have not been addressed in detail by previous research surveys. This survey aims to bring these domains holistically together, present the latest in each of these areas, highlight potential gaps and challenges, and discuss opportunities for the next generation of energy efficient systems. The survey is composed of a systematic categorization of key aspects of building energy efficient systems - (1) specification - the ability to precisely specify the power intent, attributes or properties at different layers (2) modeling and simulation of the entire system or subsystem (hardware or software or both) so as to be able to experiment with possible options and perform what-if analysis, (3) techniques used for implementing energy efficiency at different levels of the stack, (4) verification techniques used to provide guarantees that the functionality of complex designs are preserved, and (5) energy efficiency benchmarks, standards and consortiums that aim to standardize different aspects of energy efficiency, including cross-layer optimizations.

Photovoltaic sensing of a memristor based in LSMO/BTO/ITO ferroionic tunnel junctions

Memristors based on oxide tunnel junctions are promising candidates for energy efficient neuromorphic computing. However, the low power sensing of the nonvolatile resistive state is an important challenge. We report the optically induced sensing of the resistive state of a memristor based on a La0.7Sr0.3MnO3/BaTiO3/In2O3:SnO2 (90:10) heterostructure with a 3 nm thick BaTiO3 ferroelectric barrier. The nonvolatile memristive response originates from the modulation of an interfacial Schottky barrier at the La0.7Sr0.3MnO3/BaTiO3 interface, yielding robust intermediate memristive states. The Schottky barrier produces a photovoltaic response when illuminated with a 3.3 eV UV LED, which depends on the state. The open circuit voltage Voc correlates linearly with the resistance of each state, enabling active sensing of the memristive state at light power densities as low as 20 mW/cm2 and temperatures up to 100 K. This opens up avenues for the efficient and minimally invasive readout of the memory states in hybrid devices.

5G Data Offloading Using Fuzzification with Grasshopper Optimization Technique

Data offloading at the network with less time and reduced energy consumption are highly important for every technology. Smart applications process the data very quickly with less power consumption. As technology grows towards 5G communication architecture, identifying a solution for QoS in 5G through energy-efficient computing is important. In this proposed model, we perform data offloading at 5G using the fuzzification concept. Mobile IoT devices create tasks in the network and are offloaded in the cloud or mobile edge nodes based on energy consumption. Two base stations, small (SB) and macro (MB) stations, are initialized and the first tasks randomly computed. Then, the tasks are processed using a fuzzification algorithm to select SB or MB in the central server. The optimization is performed using a grasshopper algorithm for improving the QoS of the 5G network. The result is compared with existing algorithms and indicates that the proposed system improves the performance of the system with a cost of 44.64 J for computing 250 benchmark tasks.

Highly Adaptive and Energy Efficient Neuromorphic Computation Enabled by Deep-Spike Heterostructure Photonic Neuro-Transistors

Highly Adaptive and Energy Efficient Neuromorphic Computation Enabled by Deep-Spike Heterostructure Photonic Neuro-Transistors

Deep Reinforcement Learning Enabled Self-Configurable Networks-on-Chip for High-Performance and Energy-Efficient Computing Systems

Network-on-Chips (NoC) has been the superior interconnect fabric for multi/many-core on-chip systems because of its scalability and parallelism. On-chip network resources can be dynamically configured to improve the energy efficiency and performance of NoC. However, large and complex design space in heterogeneous NoC architectures becomes difficult to explore within a reasonable time for optimal trade-offs of energy and performance. Furthermore, reactive resource management is not effective in preventing problems, such as thermal hotspots, from happening in adaptive systems. Therefore, we propose machine learning techniques to provide proactive solutions within an instant in NoC-based computing systems. We present a deep reinforcement learning technique to configure voltage/frequency levels of NoC routers and links for both high performance and energy efficiency while meeting the global energy budget constraint. Distributed reinforcement learning agents technique has been proposed, where a reinforcement learning agent configures a NoC router and associated links intelligently based on system utilization and application demands. Additionally, neural networks are used to approximate the actions of distributed reinforcement learning agents. Simulations results for 256-core and 16-core NoC architectures under real applications and synthetic traffic show that the proposed self-configurable approach improves energy-delay product (EDP) by 30-40% compared to traditional non-machine-learning based solution.

Energy-Efficiency Computation Offloading Strategy in UAV Aided V2X Network With Integrated Sensing and Communication

Integrated Sensing and Communications (ISAC) technology can jointly design radio sensing and communication functionalities, which enable 6G Ere to have the ability to “see” the physical world rather than communication-only. Benefitting from ISAC, vehicular-to-everything (V2X) networks may efficiently complete high-precision traffic environment perception. Furthermore, with the assistance of flexibly deployed Unmanned Aerial Vehicles (UAVs), the V2X networks overcome the limited sensing range of sensors equipped on a vehicle and guarantee safe driving. This paper proposes an energy-efficient computation offloading strategy for multiple sensor data fusion in UAV Aided V2X Network supported by Integrated Sensing and Communication. Firstly, a vehicle-UAV cooperative perception architecture is proposed to perceive a wide range of traffic environments. Secondly, we introduce a computation offloading strategy jointly considering offloading decisions and dynamic computing resource allocation. Finally, a successive convex approximation (SCA) algorithm transforms a non-convex formulation problem into a tractable convex approximation problem. The simulation results show that the strategy proposed in this paper reduces the UAV energy consumption and data fusion task processing delay.

Teaching Learning Based Optimization (TLBO) for energy efficiency in Fog Computing

Fog Computing is eminent to ensure quality of service in handling huge volume and variety of data and to display output, or for closed loop process control. It comprises of fog devices to manage huge data transmission but results in high energy consumption, end-to end-delay, latency. In this paper, an energy model for fog computing environment has been proposed and implemented based on teacher student learning model called Teaching Learning Based Optimization (TLBO) to improve the responsiveness of the fog network in terms of energy optimization. The results show the effectiveness of TLBO in choosing the shortest path with least energy consumption.

Neuromorphic Memristive Chips: Design and Technology

Memristive neuromorphic chips exploit a prospective class of novel functional materials (memristors) to deploy a new architecture of spiking neural networks for developing basic blocks of brain-like systems. Memristor-based neuromorphic hardware solutions for multi-agent systems are considered as challenges in frontier areas of chip design for fast and energy-efficient computing. As functional materials, metal oxide thin films with resistive switching and memory effects (memristive structures) are recognized as a potential elemental base for new components of neuromorphic engineering, enabling a combination of both data storage and processing in a single unit. A key design issue in this case is a hardware defined functionality of neural networks. The gradient change of resistive properties of memristive elements and its non-volatile memory behavior ensure the possibility of spiking neural network organization with unsupervised learning through hardware implementation of basic synaptic mechanisms, such as Hebb's learning rules including spike — timing dependent plasticity, long-term potentiation and depression. This paper provides an overview of scientific researches carrying out at Saint Petersburg Electrotechnical University "LETI" since 2014 in the field of novel electronic components for neuromorphic hardware solutions of brain-like chip design. Among the most promising concepts developed by ETU "LETI" are: the design of metal-insulator-metal structures exhibiting multilevel resistive switching (gradient tuning of resistive properties and bipolar resistive switching are combined together in a sin¬gle memristive element) for further use as artificial synaptic devices in neuromorphic chips; computing schemes for spatio-temporal pattern recognition based on spiking neural network architecture implementation; breadboard models of analogue circuits of hardware implementation of neuromorphic blocks for brain-like system developing.

Using analog computers in today's largest computational challenges

Abstract. Analog computers can be revived as a feasible technology platform for low precision, energy efficient and fast computing. We justify this statement by measuring the performance of a modern analog computer and comparing it with that of traditional digital processors. General statements are made about the solution of ordinary and partial differential equations. Computational fluid dynamics are discussed as an example of large scale scientific computing applications. Several models are proposed which demonstrate the benefits of analog and digital-analog hybrid computing.