Energy-delay Product Research Articles

A Rail-To-Rail and Low Offset Novel Strongarm Comparator Circuit for Low Power Data Converter Architectures

With the rapid improvements in the design of advanced high performance communication receivers, hand-held electronic devices are in widespread usage for some time. These devices facilitate high speed and secured access to internet data. The demand for realizing a smart and better usage experience puts forth strict requirements on the design aspects of next-generation high speed low power complementary metal oxide semiconductor (CMOS) receiver design. One of the major modules in the implementation of high speed low power CMOS receiver device is the analog to digital converter (ADC) architecture. In the process of conversion from analog to digital signals, Quantization and sampling operations are vital and are realized using comparator circuits. The comparator design has a significant role in the design of data converter architecture. Several comparator architectures exist, but StrongARM topology is discussed and implemented in this work due to its negligible static power dissipation and rail to rail output voltages. The proposed novel comparator architecture is designed and simulated in 90nm CMOS process using Cadence Virtuoso tool and operated at supply voltage of VDD=1.5V, a clock frequency of 250MHz. Compared to the previous designs, the energy delay product was reduced by 8% which is an important observation to be observed for use in wireless sensor node applications.

Adaptive Web Browsing on Mobile Heterogeneous Multi-cores

Web browsing is an important application domain, but it imposes a significant power burden on mobile devices. While the heterogeneous multi-core design offers the potential for energy-efficient computing, existing web browsers fail to exploit the hardware to optimize mobile web browsing. Our work aims to offer a better way to optimize web browsing on heterogeneous mobile devices. We achieve this by developing a machine learning based approach to predict the optimal processor setting for rendering the web content. The prediction is based on the web content, the network status and the optimization goal. We evaluate our approach by applying it to the Chromium browser and testing it on a representative big.LITTLE mobile platform. We apply our approach to the top 1,000 hottest websites across seven typical networking environments. Our approach achieves over 80% of the performance delivered by a perfect predictor. Our approach achieves over 30%, 50%, and 60% improvement respectively for load time, energy consumption and the energy delay product when compared to two state-of-the arts approaches.

POWER ENERGY AND POWER AREA PRODUCT SIMULATION ANALYSIS OF MASTER-SLAVE FLIP-FLOP

Flip-flops are the fundamental building blocks of the data path structure. It is a key component of digital circuits and systems. This work offers an exclusive master-slave flip-flop topology by ensuing clocked complementary metal oxide semiconductor (C2MOS) logic, minimizing the total device count and the count of clocked devices. Reducing the number of clocked devices reduces undesirable transient activity and reduces dynamic power dissipation. C2MOS logic connects static logic design with clock signal synchronization, resulting in power savings and increased speed. The area reduction is also attained by reducing the total number of devices. The proposed topology has been realized using only sixteen transistors, including six clocked devices, resulting in area compression. Layout-level simulation at 0.12 mm C2MOS design rule technology is used to investigate the performance. According to an investigation, the proposed topology achieves power savings ranging from 19.77 to 63.75 %, area compaction ranging from 22.03 to 66.30 %, power delay product (PDP) enhancement ranging from 18.56 to 53.91 %, energy-delay product (EDP) enhancement ranging from 5.61 % to 41.39 %, power energy product (PEP) enrichment ranging from 35.63 to 82.82 %, and power area product (PAP) enrichment ranging from 35.19 to 66.30 %.

Energy-Efficient High-Speed dynamic logic-based One-Trit multiplier in CNTFET technology

The appeal of portable electronics, embedded systems, and other smart devices has been steadily growing over time. The multi-valued logic (MVL) was primarily introduced to handle the interconnect issues in binary logic. The use of ternary logic reduces the circuit complexity, power consumption in interconnects, and total chip area. The carbon nanotube field-effect transistor (CNTFET) offers some significant features like low leakage power, equal hole and electron mobility, and modulation in threshold voltage by adjusting the diameter of the carbon nanotube (CNT). In this paper, a clocked dynamic and pass transistor logic-based ternary 1-trit multiplier circuit with only 28 transistors has been proposed. The proposed logic avoids the conventional approach of using logic gates, encoder/decoder, and multiplexers, which reduces the total device count to implement the multiplier. The reduced transistor count offers a reduction in power consumption, delay, power-delay-product (PDP), and energy-delay-product (EDP) in comparison to other state-of-the-art designs. Stanford 32-nm CNTFET model file and Synopsis HSPICE simulator have been used to carry out the simulations at a supply of 0.9 V. The proposed circuit shows a 34.16 %, 66.44 %, and 82.80 % reduction in power, PDP, and EDP as compared to the lowest power, delay, and PDP of the designs under consideration. The performance of the multiplier is evaluated under different temperatures, supply voltages, loads, and oxide thickness.

Design and Performance Analysis of Logic Circuits using FinFET Technology

As the dimensions of MOSFET (Metal Oxide Semiconductor Field Effect Transistor) decreases, the short channel effect (SCE) becomes a dominating concern in VLSI. The Short channel effect causes an exponential increase in the leakage current. To reduce the SCE and hence leakage current, a new technology has been developed in recent years. In this recent technology a 3D multiple gate MOSFETs like FinFET (Fin Field Effect Transistor) has been developed which possess numerous advantages over conventional MOSFETs and has attracted many engineers and designers. FinFET is the new growing technology that works in the nm range to minimize short channel effects. Many companies (like Intel) have started using FinFET technology. This document is a review paper of current research on FinFET technology and discusses how it can be used in future to design new logic devices (like Adder, Comparator, MUX and De-MUX etc.) and memory devices. Various parameters of FinFET like reduced short channel effects, less leakage current, low power consumption, less propagation delay and less time delay are discussed. Various mathematical models and software (HSpice) were used to simulate power, delay, power delay product, average power dissipation and energy delay product. Thus, FinFET technology was designed to eliminate the problem of SCE by permitting transistors to be scaled down into sub 20nm range.

Dynamic Thermal Management of 3D Memory through Rotating Low Power States and Partial Channel Closure

Modern high-performance and high-bandwidth three-dimensional (3D) memories are characterized by frequent heating. Prior art suggests turning off hot channels and migrating data to the background DDR memory, incurring significant performance and energy overheads. We propose three Dynamic Thermal Management (DTM) approaches for 3D memories, reducing these overheads. The first approach, Rotating-channel Low-power-state-based DTM (RL-DTM) , minimizes the energy overheads by avoiding data migration. RL-DTM places 3D memory channels into low power states instead of turning them off. Since data accesses are disallowed during low power state, RL-DTM balances each channel’s low-power-state duration. The second approach, Masked rotating-channel Low-power-state-based DTM (ML-DTM) , is a fine-grained policy that minimizes the energy-delay product (EDP) and improves the performance of RL-DTM by considering the channel access rate. The third strategy, Partial channel closure and ML-DTM , minimizes performance overheads of existing channel-level turn-off-based policies by closing a channel only partially and integrating ML-DTM, reducing the number of channels being turned off. We evaluate the proposed DTM policies using various mixes of SPEC benchmarks and multi-threaded workloads and observe them to significantly improve performance, energy, and EDP over state-of-the-art approaches for different 3D memory architectures.

Gibbon: An Efficient Co-Exploration Framework of NN Model and Processing-In-Memory Architecture

The memristor-based Processing-In-Memory (PIM) architectures have been proven to be a potential architecture to store enormous parameters and execute the complicated computations of Deep Neural Networks (DNNs) efficiently. Existing PIM studies focus on designing high energy-efficient hardware architecture and algorithm-hardware co-optimization for better performance. However, the impacts of the algorithms and hardware architectures on the performance intersect with each other. Only optimizing the algorithms or the hardware architectures can not realize the optimal design. Therefore, the co-exploration of NN models and PIM architecture is necessary. However, for one thing, the co-exploration space size of NN models and PIM architectures is extremely huge, and is challenging to search. For another, during the co-exploration process, time-consuming PIM simulators are needed to evaluate various design candidates and pose a heavy time burden. To tackle these problems, we propose an efficient co-exploration framework of NN models and PIM architectures, named . In, the co-exploration space is carefully designed to adapt both NN models and PIM architectures. Besides, in order to improve search efficiency, we propose an evolutionary search algorithm with adaptive parameter priority (ESAPP). In addition, introduces a multi-level joint simulator to alleviate the problem of time-consuming evaluation. The experimental results show that the proposed co-exploration framework can find better NN models and PIM architectures than existing studies in only six GPU hours (9.8 48.2× speedup). At the same time, can improve the accuracy of co-design results by 15.3% and reduce the energy-delay-product (EDP) by 5.96× compared with existing work.

Theoretical Validation and Hardware Implementation of Dynamic Adaptive Scheduling for Heterogeneous Systems on Chip

Domain-specific systems on chip (DSSoCs) aim to narrow the gap between general-purpose processors and application-specific designs. CPU clusters enable programmability, whereas hardware accelerators tailored to the target domain minimize task execution times and power consumption. Traditional operating system (OS) schedulers can diminish the potential of DSSoCs, as their execution times can be orders of magnitude larger than the task execution time. To address this problem, we propose a dynamic adaptive scheduling (DAS) framework that combines the advantages of a fast, low-overhead scheduler and a sophisticated, high-performance scheduler with a larger overhead. We present a novel runtime classifier that chooses the better scheduler type as a function of the system workload, leading to improved system performance and energy-delay product (EDP). Experiments with five real-world streaming applications indicate that DAS consistently outperforms fast, low-overhead, and slow, sophisticated schedulers. DAS achieves a 1.29× speedup and a 45% lower EDP than the sophisticated scheduler under low data rates and a 1.28× speedup and a 37% lower EDP than the fast scheduler when the workload complexity increases. Furthermore, we demonstrate that the superior performance of the DAS framework also applies to hardware platforms, with up to a 48% and 52% reduction in the execution time and EDP, respectively.

Simulation and Characterization of Carbon Nanotube-based 2:1 Multiplexer Electrical Properties

This paper reports on using simulation to characterize a Carbon Nanotube (CNT) based 2:1 multiplexer (MUX). This study aimed to evaluate the electrical properties, particularly the propagation delay, average power consumption, Power-Delay Product (PDP), and Energy-Delay Product (EDP). Different design approaches namely conventional CMOS, Pass Transistor Logic (PTL) approach, and Gate Diffusion Input (GDI) were adopted. The voltage supply (VDD) and diameter of the CNT are varied to see the effect on the electrical properties. The simulation was carried out using HSPICE. Through simulation, it is found that the GDI approach used the least number of transistors followed by PTL and CMOS. The calculation of the propagation delay exhibits a substantial improvement of more than 95% using the GDI approach. The average power consumption shows a 55.30% and 35.16% reduction when compared to CMOS and PTL respectively. The PDP demonstrates an improvement of more than 95% when compared with conventional CMOS and PTL approaches. The same trend of observation is also achieved for EDP. The variation of the VDD and chirality has a markable effect on the propagation delay and average power consumption. This is a preliminary attempt to evaluate the performance of CNT implementation in MUX. The outcome can become the guideline for engineers working in circuit design using emerging materials for future nanoelectronics applications.

Flexible and Scalable BLAKE/BLAKE2 Coprocessor for Blockchain-Based IoT Applications

Developing flexible, high-processing-rate, and low-power BLAKE/BLAKE2 hardware is extremely necessary for maintaining dependability, safety, and security in blockchain-based IoT systems. However, the existing hardware designs are difficult to achieve high flexibility and performance with high hardware efficiency. Therefore, this paper proposes the first flexible and scalable BLAKE/BLAKE2 coprocessor to gain high flexibility, high performance, and low power for blockchain-based IoT applications. To achieve those goals, three novel optimization techniques are proposed, including a dual-core hashing engine, a pipelined hashing engine, and a scalable four-engine coprocessor. The experimental results on FPGA and ASIC prove that our coprocessor is 3.6-65.5 times, 1.4-2.9 times, and 113-195 times better than existing works in throughput, area efficiency, and energy efficiency, respectively. Additionally, our coprocessor supports more hash functions, making it more flexible than previous architectures. Besides, the proposed coprocessor outperforms the industrial CPU/GPU by 4.7-7.1 times in the energy-delay product (EDP).

A Novel Adaptive UE Aggregation-Based Transmission Scheme Design for a Hybrid Network with Multi-Connectivity

With the progress of the eras and the development of science and technology, the requirements of device-to-device (D2D) connectivity increased rapidly. As one important service in future systems, ultra-reliable low-latency communication (URLLC) has attracted attention in many applications, especially in the Internet of Things (IoT), smart cities, and other scenarios due to its characteristics of ultra-low latency and ultra-high reliability. However, in order to achieve the requirement of ultra-low latency, energy consumption often increases significantly. The optimization of energy consumption and the latency of the system in the communication field are often in conflict with each other. In this paper, in order to optimize the energy consumption and the latency jointly under different scenarios, and since the detailed requirements for latency and reliability are diverse in different services, we propose an adaptive UE aggregation (AUA)-based transmission scheme that explores the diversity gain of multiple simultaneous paths to reduce the overall latency of data transmission, wherein multiple paths correspond to multiple coordination nodes. Furthermore, it could provide the feasibility of link adaptation by adjusting the path number according to the real transmission environment. Then, unnecessary energy waste could be avoided. To evaluate the performance, the energy-delay product (EDP) is proposed for the latency and energy comparison. The provided simulation results align with the numerical data. Through the analysis, it can be proven that the proposed scheme can achieve a joint optimization of latency and energy consumption to meet different types of URLLC services.

Computationally Efficient DNN Mapping Search Heuristic using Deep Reinforcement Learning

In this work, we present a computationally efficient Reinforcement Learning mapping search heuristic for finding high quality mappings for N-dimensional convolution loops that uses a computationally inexpensive reward function based on potential data reuse of operands to guide the search process. We also present a RL state representation generalizable to N-dimensional convolution loops, and a state representation parsing strategy ensuring that only valid mappings are evaluated for quality. Our RL search heuristic is applicable to multi-core systems with a memory hierarchy. We show that our RL based search heuristic for a range of 3D convolution layers, at significantly lower computational expense than random search, generally yields mappings with lower Energy-Delay Product (EDP) for an architecture with multiple processing elements with shared memory connected to DRAM. Our evaluation results demonstrated across 19 3D convolution layers, shows that our RL method performed only an average 11.24% of the operations of that of Timeloop’s random search for assessing same number of valid mappings. The mappings found using Timeloop had an average 12.51% higher EDP compared to lowest EDP mapping found using our RL method. Further, the lowest EDP mappings found using our method had an average only 4.69× higher EDP than the theoretical lower bound EDP, with the best case being only 1.29× higher.

Dynamic Power Management in Large Manycore Systems: A Learning-to-Search Framework

The complexity of manycore System-on-chips (SoCs) is growing faster than our ability to manage them to reduce the overall energy consumption. Further, as SoC design moves toward three-dimensional (3D) architectures, the core's power density increases leading to unacceptable high peak chip temperatures. In this article, we consider the optimization problem of dynamic power management (DPM) in manycore SoCs for an allowable performance penalty (say, 5%) and admissible peak chip temperature. We employ a machine learning– (ML) based DPM policy, which selects the voltage/frequency levels for different cluster of cores as a function of the application workload features such as core computation and inter-core traffic, and so on. We propose a novel learning-to-search (L2S) framework to automatically identify an optimized sequence of DPM decisions from a large combinatorial space for joint energy-thermal optimization for one or more given applications. The optimized DPM decisions are given to a supervised learning algorithm to train a DPM policy, which mimics the corresponding decision-making behavior. Our experiments on two different manycore architectures designed using wireless interconnect and monolithic 3D demonstrate that principles behind the L2S framework are applicable for more than one configuration. Moreover, L2S-based DPM policies achieve up to 30% energy-delay product savings and reduce the peak chip temperature by up to 17 °C compared to the state-of-the-art ML methods for an allowable performance overhead of only 5%.

FeCrypto: Instruction Set Architecture for Cryptographic Algorithms Based on FeFET-Based In-Memory Computing

Recently, computing-in-memory (CiM) becomes a promising technology for alleviating the memory wall bottleneck. CiM is suitable for data-intensive applications, especially cryptographic algorithms. Most current cryptographic accelerators are specific to a single function. It is expensive to accelerate different cryptographic algorithms with different accelerators. In this work, we first introduce a CiM architecture FeMIC that supports multi-operand CiM operations, by exploring advantages of state-of-the-art ferroelectric field-effect transistors. Based on that, we propose a novel instruction set together with an accelerator architecture named FeCrypto which supports the acceleration of various cryptographic algorithms. Evaluation results show that FeCrypto has better performance and energy efficiency than software implementations. The energy-delay product (EDP) of FeCrypto is 118.4× and 1.93× lower than that of the dedicated AES accelerator AIM that is built based on phase-change memories (PCMs) and magnetic random-access memories (MRAMs), respectively. EDP is reduced by 44.7× compared with PCM-based EIM, a recent AES accelerator. Compared with MRAM-based EIM, the EDP overhead of FeCrypto for supporting multiple functions is 23.2%.

Time–Energy Correlation for Multithreaded Matrix Factorizations

The relationship between time and energy is an important aspect related to energy savings in modern multicore architectures. In this paper, we investigated and analyzed the correlation between time and energy. We compared the execution time and energy consumption of the LU factorization algorithms (versions with and without pivoting) and Cholesky with the Math Kernel Library (MKL) on a multicore machine. To reduce the energy of these multithreaded factorizations, the Dynamic Voltage and Frequency Scaling (DVFS) technique was used. This technique allows the clock frequency to be scaled without changing the implementation. In particular, we studied the correlations between time and energy using two metrics: Energy Delay Product (EDP) and Greenup, Powerup, and Speedup (GPS-UP). An experimental evaluation was performed on an Intel Xeon Gold multicore machine as a function of the number of threads and the clock speed. Our test results showed that scalability in terms of execution time, expressed by the Speedup metric, had values close to a linear function as the number of threads increased. In contrast, the scalability in terms of energy consumption, expressed by the Greenup metric, had values close to a logarithmic function as the number of threads increased. The use of the EDP and GPS-UP metrics allowed us to evaluate the impact of the optimized code (DVFS and increase in the number of threads) on the time and energy consumption and to determine a better green category representing energy savings without losing performance.

Performance analysis of Cu-MWCNT bundled HCTSVs using ternary logic

This paper presents an investigation of crosstalk issues for coupled heterogeneous coaxial through silicon vias (HCTSVs) in ternary logic. Crosstalk issues are investigated for coupled HCTSVs using Cu-MWCNT as a conductive filler and polymer liners such as polyimide, polypropylene carbonate (PPC), and benzocyclobutene (BCB) as insulating materials. The electrical equivalent circuit model is utilized to investigate the crosstalk induced by the ternary inverter in coupled HCTSVs. The effects of crosstalk such as functional and dynamic crosstalk for proposed HCTSVs are compared with Multi-walled CNT (MWCNT) TSVs using Hewlett simulation program with integrated circuit emphasis (HSPICE) simulations. Other performance parameters are also investigated, including power dissipation, power delay product (PDP), and energy delay product (EDP). The proposed model's crosstalk effects are also investigated for various TSV heights. The BCB-based coupled Cu-MWCNT HCTSVs provide a significant improvement in crosstalk at reduced TSV height. The proposed HCTSVs also improved overall performance by 32.12% when compared to the MWCNT based TSVs. As a result, Cu-MWCNT based HCTSVs with BCB liner are better than conventional TSVs for ternary logic integrated circuits (ICs).

ADRA: Extending Digital Computing-In-Memory With Asymmetric Dual-Row-Activation

Computing in-memory (CiM) has emerged as an attractive technique to mitigate the von-Neumann bottleneck. Current digital CiM approaches for in-memory operands are based on multi-wordline assertion for computing bit-wise Boolean functions and arithmetic functions such as addition. However, most of these techniques, due to the many-to-one mapping of input vectors to bitline voltages, are limited to CiM of commutative functions, leaving out an important class of computations such as subtraction. In this paper, we propose a CiM approach, which solves the mapping problem through an asymmetric wordline biasing scheme, enabling (a) simultaneous single-cycle memory read and CiM of primitive Boolean functions (b) computation of any Boolean function and (c) CiM of non-commutative functions such as subtraction and comparison. While the proposed technique is technology-agnostic, we show its utility for ferroelectric transistor (FeFET)-based non-volatile memory. Compared to the standard near-memory methods (which require two full memory accesses per operation), we show that our method can achieve a full scale two-operand digital CiM using just one memory access, leading to a 23.2% -72.6% decrease in energy-delay product (EDP).

Vincent: Green hot methods in the JVM

In this paper, we show the energy efficiency of Java applications can be improved by applying Dynamic Voltage and Frequency Scaling (DVFS) inside the Java Virtual Machine (JVM). We augment the JVM to record the energy consumption of hot methods as the underlying CPU is run at different clock frequencies; after all the frequency possibilities for a method have been explored, the execution of the method in an optimized run is set to the CPU frequency that leads to the most energy-efficient execution for that method. We introduce a new sampling methodology to overcome the dual challenges in our design: both the underlying measurement mechanism for energy profiling and the DVFS for energy optimization are overhead-prone. We extend JikesRVM with our approach and benchmark it over the DaCapo suite on a server-class Linux machine. Experiments show we are able to use 14.9% less energy than built-in power management in Linux, and improve energy efficiency by 21.1% w.r.t. the metric of Energy-Delay Product (EDP).

FDSOI-Based Analog Computing for Ultra-Efficient Hamming Distance Similarity Calculation

Computing the similarity between two binary strings is a frequently used operation in cryptography, machine learning, and other areas. The Hamming distance is a simple yet costly to compute similarity metric. A common way is to XOR both binary input strings and then count the number of 1s. Especially the latter popcount part is inefficient with purely digital circuits. In this paper, a novel analog circuit is proposed to compute the Hamming distance in an ultra-efficient way. Contrary to the major trend in the state of the art, no emerging technology is required. Instead, the unique feature of the mature FDSOI transistor technology is exploited for the first time to perform analog-based similarity calculation. Thanks to the additional back gate available in this technology, the transistor’s threshold voltage can be modulated by more than 1. Through this key feature, an ultra-efficient analog computing is realized, replacing the inefficient digital popcount traditionally built from expensive adder tree structures. The design is evaluated with an FDSOI transistor model calibrated with industrial measurements. The energy-delay product is at least 24 smaller than purely digital implementations and the transistor count is reduced by over 2.6.

High-performance ternary designs using graphene nanoribbon transistors

Considering the issues emerging because of shrinking silicon field effect transistors (FETs), various post-silicon, post-binary logics are investigated by the researchers. The design of ternary schematics utilizing graphene nanoribbon FET (GNRFET) circuits is one alternate option. Since different threshold voltages are obtained by employing GNRFETs by varying its physical dimension, GNRFET is an ideal option for designing ternary circuits. The ternary circuit designs such as adder, subtractor and multiplier using GNRFETs are proposed in this study. These designs are developed using the ternary based decoder circuit. The proposed circuits are developed and executed in Synopsys based HSPICE simulator for functional verification. Additionally, the performances such as delay, power, power-delay-product (PDP) and energy-delay-product (EDP) of the proposed circuits are investigated and compared to CNTFET based ternary designs. The GNRFET ternary designs improved the performance on an average up to 30.96% than the CNTFET based designs.