Memory Endurance Research Articles

에너지 소비 및 메모리 내구성을 고려한 EEPROM-SRAM 하이브리드 비휘발성 카운터의 설계 공간 탐색

에너지 소비 및 메모리 내구성을 고려한 EEPROM-SRAM 하이브리드 비휘발성 카운터의 설계 공간 탐색

Impact of LPCVD TEOS Thickness on Vt-Pushout in Flash Memory Cell due to Mechanical Stress

This paper reports on the dependence of cycling or endurance in flash memory with the stress induced by low-pressure chemical vapor deposition (LPCVD) process. The deposited 12.5nm tetraethyl orthosilicate (TEOS) layer served as sacrificial oxide during source/drain (S/D) implantation, which was then subsequently removed. However, this deposited TEOS layer has been found to induce a stress on the channel which affects the flash memory cycling or endurance performance.

Effect of electrode material on characteristics of non-volatile resistive memory consisting of Ag2S nanoparticles

In this study, Ag2S nanoparticles are synthesized and used as the active material for two-terminal resistance switching memory devices. Sintered Ag2S films are successfully crystallized on plastic substrates with synthesized Ag2S nanoparticles, after a relatively low-temperature sintering process (200 °C). After the sintering process, the crystallite size is increased from 6.8 nm to 80.3 nm. The high ratio of surface atoms to inner atoms of nanoparticles reduces the melting point temperature, deciding the sintering process temperature. In order to investigate the resistance switching characteristics, metal/Ag2S/metal structures are fabricated and tested. The effect of the electrode material on the non-volatile resistive memory characteristics is studied. The bottom electrochemically inert materials, such as Au and Pt, were critical for maintaining stable memory characteristics. By using Au and Pt inert bottom electrodes, we are able to significantly improve the memory endurance and retention to more than 103 cycles and 104 sec, respectively.

Fully Exploiting PCM Write Capacity Within Near Zero Cost Through Segment-Based Page Allocation

Improving the endurance of phase change memory (PCM) is a fundamental issue when PCM technology is considered as an alternative to main memory usage. Existing wear-leveling techniques overcome this challenge through constantly remapping hot virtual pages, thus engendering a fair amount of extra write operations to PCM and imposing considerable performance and energy overhead. Our observation is that it is unnecessary to fully balance the accesses to different physical page frames during the execution of each process. Instead, since endurance is a lifetime factor, the hot virtual pages of different processes can be mapped to different physical pages in the PCM. Leveraging this property, we develop a wear-resistant page allocation algorithm, which exploits the diverse write characteristics of different program segments to improve PCM write endurance within almost no extra remapping cost in terms of energy and performance. The results of experiments conducted based on SPEC benchmarks show that the proposed technique can prolong PCM lifetime by hundreds of times within nearly zero searching and remapping overhead.

Reducing Data Migration Overheads of Flash Wear Leveling in a Progressive Way

As the endurance of flash memory keeps deteriorating, exploiting wear leveling (WL) techniques to improve the lifetime/endurance of flash memory has become a critical issue in the design of flash storage devices. Nevertheless, the deteriorated access performance of high-density flash memory makes the performance overheads introduced by WL non-negligible. In particular, the existing WL designs usually aggressively distribute the erases to all flash blocks evenly in a regular basis. As a result, a lot of non-negligible unnecessary data migrations would be imposed in the early stages of the device lifespan, and would be further exacerbated if a WL design selects improper victim blocks for erases. In contrast to the existing WL approaches, we propose a progressive WL design to perform WL in a progressive way to prevent any block from being worn out prematurely with minimized performance overheads caused by the unnecessary data migration. The experiments were conducted based on representative realistic workloads to evaluate the efficacy of the proposed design. The results reveal that instead of sacrificing the device lifetime, performing WL in such a progressive way can not only minimize the performance overheads but also have potentials to extend the device lifetime.

Effective Lifetime-Aware Dynamic Throttling for NAND Flash-Based SSDs

NAND flash-based solid-state drives (SSDs) are increasingly popular in enterprise server systems because of their advantages over hard disk drives such as higher performance and lower power consumption. However, the decreasing write endurance and the unpredictable lifetime remains to be a serious obstacle to their wider adoption in enterprise systems. In this paper, we propose effective lifetime-aware dynamic throttling, called LADY, which guarantees the required storage lifetime by intentionally throttling the write performance of SSDs with consideration of the effective write endurance of NAND flash memory. Unlike existing static throttling, LADY makes throttling decisions based on the characteristics of a workload so that the required SSD lifetime can be guaranteed with less performance degradation. LADY also exploits the improvement on write endurance depending on the NAND program speed and the recovery effects of floating-gate transistors, thereby maximally utilizing the available write endurance of NAND flash while mitigating the decreasing write endurance problem. Our experimental results show that LADY improves write performance by 4.7x with small write response time variations over existing static throttling while guaranteeing the required SSD lifetime.

Enhancement of a cyclic endurance of phase change memory by application of a high-density C15(Ge21Sb36Te43) film

The lower cyclic endurance of Phase Change Memory (PCM) devices limits the spread of its applications for reliable memory. The findings reported here show that micro-voids and excess vacancies that are produced during the deposition process and the subsequent growth in sputtered carbon-doped GeSbTe films is one of the major causes of device failure in PCM with cycling. We found that the size of voids in C15(Ge21Sb36Te43) films increased with increasing annealing temperature and the activation energy for the growth rate of voids was determined to be 2.22 eV. The film density, which is closely related to voids, varies with the deposition temperature and sputtering power used. The lower heat of vaporization of elemental Sb and Te compared to that for elemental Ge and C is a major cause of the low density of the film. It was possible to suppress void formation to a considerable extent by optimizing the deposition conditions, which leads to a dramatic enhancement in cyclic endurance by 2 orders of magnitude in PCM devices prepared at 300oC-300W compared to one prepared at 240oC-500W without change of compositions.

Retention Trimming for Lifetime Improvement of Flash Memory Storage Systems

NAND flash memory has been widely deployed in embedded systems, personal computers, and data centers. While recent technology scaling and density improvement have reduced its price, they have also significantly shortened its endurance. In this paper, with the understanding of the relationship between data retention time and flash wearing, a retention trimming approach, which trims data retention time based on the data lifetime, is proposed to reduce the wearing of flash memory, and hence improve the endurance of flash memory. Extensive experimental results show that the proposed technique achieves significant endurance improvements.

Copper Ion-containing Ionic Liquids Provide Improved Endurance and Switching Voltage Distributions of Conducting-bridge Random Access Memory

Abstract Remarkable improvement of cycling endurance and working voltage variance has been achieved by the addition of a trace amount of a [bmim][Tf2N] solution containing Cu(Tf2N)2 to the HfO2 film layer of a CB-RAM with a Cu/HfO2/Pt structure.

True-Damage-Aware Enumerative Coding for Improving <sc>nand</sc> Flash Memory Endurance

This brief presents a technique that can fully exploit the data dependency of flash memory cell damage to improve the program/erase (P/E) cycling endurance of nand flash memory. The key is to opportunistically leverage data lossless compressibility and utilize the compression gain to realize memory-damage-aware data manipulation to reduce the cycling-induced physical damage. Based upon experiments using commercial sub-22-nm MLC nand flash memory chips, we show that the proposed design technique can improve the P/E cycling endurance by 50%. We further carried out application-specific integrated circuit design to demonstrate the practical feasibility for implementing the proposed design technique.

A Unique Approach to Generate Self-Aligned SiO2/Ge/SiO2/SiGe Gate-Stacking Heterostructures in a Single Fabrication Step.

We report a first-of-its-kind, unique approach for generating a self-aligned, gate-stacking heterostructure of Ge quantum dot (QD)/SiO2/SiGe shell on Si in a single fabrication step. The 4-nm-thick SiO2 layer between the Ge QD and SiGe shell fabricated during the single-step process is the result of an exquisitely controlled dynamic balance between the fluxes of oxygen and silicon interstitials. The high-quality interface properties of our “designer” heterostructure are evidenced by the low interface trap density of as low as 2–4 × 1011 cm−2 eV−1 and superior transfer characteristics measured for Ge-based metal-oxide-semiconductor field-effect transistors (MOSFETs). Thanks to the very thin interfacial SiO2 layer, carrier storage within the Ge QDs with good memory endurance was established under relatively low-voltage programming/erasing conditions. We hope that our unique self-aligned, gate-stacking heterostructure provides an effective approach for the production of next-generation, high-performance Ge gate/SiO2/SiGe channel MOSFETs.

Improving resistance uniformity and endurance of resistive switching memory by accurately controlling the stress time of pulse program operation

In this letter, the impact of stress time of pulse program operation on the resistance uniformity and endurance of resistive random access memory (RRAM) is investigated. A width-adjusting pulse operation (WAPO) method which can accurately setup and measure switching time is proposed for improving the uniformity and endurance of RRAM. Different from the traditional single pulse operation (TSPO) method in which only one wide pulse is applied in each switching cycle, WAPO method utilizes a series of pulses with the width increased gradually until a set or reset switching process is completely finished and no excessive stress is produced. Our program/erase (P/E) method can exactly control the switching time and the final resistance and can significantly improve the uniformity, stability, and endurance of RRAM device. Improving resistance uniformity by WAPO compared with TSPO method is explained through the interdependence between resistance state and switching time. The endurance improvement by WAPO operation stems from the effective avoidance of the overstress-induced progressive-breakdown and even hard-breakdown to the conductive soft-breakdown path.

Concatenated BCH and LDPC Coding Scheme With Iterative Decoding Algorithm for Flash Memory

As adopting a very powerful error-correcting code gradually becomes a strategic demand for the endurance of nowadays flash memory, LDPC codes are recently proposed due to their outstanding error correcting capability. However, the error floor phenomenon of LDPC codes might not meet the extreme low error rate requirement of flash memory applications. Thus, concatenation of BCH and LDPC codes that strikes a balance between superb error correcting capability and low error floor becomes an alternative system structure. In this work, a modification of such concatenated coding system in Chen et al. [IEEE Commun. Lett., vol. 17, no. 5, pp. 980–983, May 2013] is proposed. Compared with the previous concatenated coding system via simulations, our design improves the error correcting capability in the waterfall region while keeps low error floor.

Wear Relief for High-Density Phase Change Memory Through Cell Morphing Considering Process Variation

Due to the scalability and large leakage power, dynamic random-access memory (DRAM) has a lot of challenges in scaling. As an alternative, phase change memory (PCM) has demonstrated promising potential to serve as the main memory in deep submicrometer regime. The broad resistance range of PCM cells enables several cell modes with various densities, pertaining to multiple level cell (MLC), triple state cell (TSC), and single level cell (SLC). High-density mode outperforms low-density ones in terms of capacity and cost-per-bit, but suffers from a weaker cell endurance. Wear leveling strategies are proposed to enhance the memory endurance but encounter more challenges with the aggravating process variation. Due to endurance variations, physical domains are fabricated with irregular tenacity. As a result, balanced write traffic, which is the objective of traditional wear leveling, cannot fully exploit the PCM endurance since the weak parts will be worn out sooner than others. In this paper, considering process variation, we propose a cell morphing based wear leveling scheme. Cell morphing refers to the cell mode transformation between high density (e.g., MLC) and low densities (e.g., TSC and SLC). Instead of redistributing write operations, the proposed wear leveling scheme dynamically transforms weak and frequently written portions into low-density mode for endurance benefits. Multitier cell morphing schemes are proposed to support mode transformation among multiple density levels. The experimental results show 236% endurance improvement for single-tier cell morphing and 209% for two-tier cell morphing with 2% low-density page percentage, when compared with the most related work.

NAND Flash Memory Organization and Operations

NAND flash memories are well known for their uncomplicated structure, low cost, and high capacity. Their typical characteristics include architecture, sequential reading, and high density. NAND flash memory is a non-volatile type of memory and has low power consumption. The erasing of NAND Flash memory is based on a block-wise base. Since cells in a flash chip will fail after a limited number of writes, limited write endurance is a key characteristic of flash memory. There are many noise causes such as read or program disturbs, retention process, charge leakage, trapping generation, etc. Preferably, all errors in the storage would be adjusted by the ECC algorithm. The conclusion of all mentioned parasitic factors creates a set of external and internal influences which affects variable behaviour of memory in time. To prepare a review of all the important factors that affect the reliability and life-cycle endurance of NAND flash memories and was our main motivation for this paper.

Medial prefrontal cortex dopamine controls the persistent storage of aversive memories.

Medial prefrontal cortex (mPFC) is essential for initial memory processing and expression but its involvement in persistent memory storage has seldom been studied. Using the hippocampus dependent inhibitory avoidance learning task and the hippocampus-independent conditioned taste aversion paradigm together with specific dopamine receptor agonists and antagonists we found that persistence but not formation of long-term aversive memories requires dopamine D1/D5 receptors activation in mPFC immediately after training and, depending on the task, between 6 and 12 h later. Our results indicate that besides its well-known participation in retrieval and early consolidation, mPFC also modulates the endurance of long-lasting aversive memories regardless of whether formation of the aversive mnemonic trace requires the participation of the hippocampus.

Write-Aware Replacement Policies for PCM-Based Systems

The gap between processor and memory speeds is one of the greatest challenges that current designers face in order to develop more powerful computer systems. In addition, the scalability of the Dynamic Random Access Memory (DRAM) technology is very limited nowadays, leading one to consider new memory technologies as candidates for the replacement of conventional DRAM. Phase-Change Memory (PCM) is currently postulated as the prime contender due to its higher scalability and lower leakage. However, compared with DRAM, PCM also exhibits some drawbacks, like lower endurance or higher dynamic energy consumption and write latency, that need to be mitigated before it can be used as the main memory technology for the next generation of computers. This work addresses the PCM endurance constraint. For this purpose, we present an analysis of conventional cache replacement policies in terms of the amount of writebacks to main memory that they imply and we also propose some new replacement algorithms for the last-level cache (LLC) with the goal of cutting down the write traffic to memory and consequently, to increase PCM lifetime without degrading system performance. In this paper, we target general purpose processors provided with this kind of non-volatile main memory and we exhaustively evaluate our proposed policies in both single- and multi-core environments. Experimental results show that, on average, compared with a conventional Least Recently Used (LRU) algorithm, some of our proposals manage to reduce the amount of writes to main memory up to 20–30% depending on the scenario evaluated, which leads to memory endurance extensions of up to 20–45%, also reducing the energy consumption in the memory hierarchy by up to 9% and hardly degrading performance.

Approximate Storage in Solid-State Memories

Memories today expose an all-or-nothing correctness model that incurs significant costs in performance, energy, area, and design complexity. But not all applications need high-precision storage for all of their data structures all of the time. This article proposes mechanisms that enable applications to store data approximately and shows that doing so can improve the performance, lifetime, or density of solid-state memories. We propose two mechanisms. The first allows errors in multilevel cells by reducing the number of programming pulses used to write them. The second mechanism mitigates wear-out failures and extends memory endurance by mapping approximate data onto blocks that have exhausted their hardware error correction resources. Simulations show that reduced-precision writes in multilevel phase-change memory cells can be 1.7 × faster on average and using failed blocks can improve array lifetime by 23% on average with quality loss under 10%.

Increasing Endurance and Security of Phase-Change Memory with Multi-Way Wear-Leveling

Phase-change memory (PCM) is a promising alternative of DRAM. Nonetheless, it has a well-known problem that is the limited number of writes to storage cells. Thus, wear-leveling, which makes the writes uniform, is crucial to boost PCM's lifetime. This paper proposes multi-way wear leveling (MWWL) to increase both endurance and security of PCM. MWWL can efficiently distribute writes to physical addresses uniformly from a multiple of ways while incurring little write overhead and almost no extra hardware overhead. More important, MWWL is a fundamental scheme that can be applied to existing leveling algorithms. As a case study, we extended a state-of-the-art technique, Security Refresh, to its multi-way version, Multi-Way Security Refresh (MWSR). The experimental results show that MWSR can achieve the same or better lifetime than that of the original two-level Security Refresh but with much less write overhead (from 11.7% down to 1.5%).

Lifetime-Aware Capacity Dynamic Adjusting for Solid State Disk

In this paper, we analyzed the endurance of Nand Flash memory and then proposed a level adjusting scheme to use the MLC Flash dynamically to storage different amount of data levels through the entire lifetime. The result shows that the MLC SSD adopting this method could be totally written 4.8X more data than conventional MLC SSD and 16.5% more than SLC SSD.