Increasing Endurance and Security of Phase-Change Memory with Multi-Way Wear-Leveling

Abstract

Phase-change memory (PCM) is a promising alternative of DRAM. Nonetheless, it has a well-known problem that is the limited number of writes to storage cells. Thus, wear-leveling, which makes the writes uniform, is crucial to boost PCM's lifetime. This paper proposes multi-way wear leveling (MWWL) to increase both endurance and security of PCM. MWWL can efficiently distribute writes to physical addresses uniformly from a multiple of ways while incurring little write overhead and almost no extra hardware overhead. More important, MWWL is a fundamental scheme that can be applied to existing leveling algorithms. As a case study, we extended a state-of-the-art technique, Security Refresh, to its multi-way version, Multi-Way Security Refresh (MWSR). The experimental results show that MWSR can achieve the same or better lifetime than that of the original two-level Security Refresh but with much less write overhead (from 11.7% down to 1.5%).