Efficient Wear Leveling for PCM/DRAM-Based Hybrid Memory

Abstract

Phase change memory (PCM) has emerged as a promising candidate for next-generation storage media, owing to its low power consumption, non-volatility, and high scalability. However, PCM has limited write endurance, or more particularly, it can only undergo a limited number of wearing operations. This problem is much critical to the lifetime of PCM. Aiming to solve this problem, in this paper we propose an efficient wear leveling design for PCM/DRAM-based hybrid memory systems, which is able to balance the write operations to PCM and lengthen the lifetime of PCM. In particular, we first propose a new architecture called MH-BS (MinHeap Buddy System) for PCM/DRAM-based hybrid memory, in which DRAM and PCM are both employed as main memory. Next, we propose two new structures to management the spaces of PCM, namely a minimum heap array (MinHeap-Array) and a wear-skewed array (WearSkew-Array). We devise efficient algorithms for memory allocation and reclaim based on the proposed structures. With these mechanisms, write operations are distributed to PCM chips in a balanced manner and the write amplification ratio of PCM incurred by page swaps is reduced, yielding a better wear leveling for PCM and longer lifetime of PCM. Our experimental results on a simulated PCM/DRAM-based hybrid memory system and four kinds of workloads show that our proposal is efficient for the wear leveling of PCM, and thus offers a more practical solution for the memory management on PCM/DRAM-based hybrid memory systems.