Polysilicon Emitter Research Articles

VES-BJT: A Lateral Bipolar Transistor on SOI with Polysilicon Emitter and Collector

This paper summarizes the results of investigations of bipolar transistors made in VESTIC (Vertical Slit Transistor-based Integrated Circuits) technology. This technology was proposed by W. Maly as an alternative to classical bulk CMOS technology. However, the basic VESTIC cell can be used not only to make field effect transistors but also to make bipolar transistors. Their structures differ in many ways from existing structures of bipolar transistors. The investigations reported here aim to answer the question: can VESTIC-based lateral bipolar transistors be useful as active devices, and can they be made technologically compatible with field effect VESTIC devices? The theoretical studies were followed by the fabrication and measurements of VESTIC-based p-n-p and n-p-n bipolar devices. Although the manufacturing technology available was far from optimal, working bipolar devices were obtained. The results show that VESTIC-based bipolar devices may achieve acceptable parameters if made with state-of-the-art manufacturing technology. The main outcome of the research reported in the paper is that p-n-p and n-p-n bipolar transistors with acceptable parameters may be fabricated, together with field effect devices, in VESTIC-based integrated circuits. As a result, the VESTIC technology could become the new original BiCMOS technology.

New Insights Into Noise Characteristics of Hot Carrier Induced Defects in Polysilicon Emitter Bipolar Junction Transistors and SiGe HBTs

Low frequency (LF) noise is a powerful and nondestructive technique for evaluating the oxide-semiconductor interface and an effective evaluating tool in characterizing electronic device’s structure and reliability. In this study, we present a systematic analysis of the striking abnormal 1/f noise behavior of the hot carrier induced defects in highspeed polysilicon emitter bipolar transistors (PE-BJTs) and SiGe HBTs. Here, the comparative results before and after hot carrier degradation reveal that low frequency noise spectra are not correlated with the density and distribution of the interfacial defects, which related to Si dangling bonds reside at the SiO2/Si interface in PE-BJTs and SiGe HBTs.

Time-Dependent Hot Carrier Degradation in Polysilicon Emitter Bipolar Transistors Under High Current and Radiation Combined Stress

A comparative combined stress-induced reliability issues between Auger hot carrier and ionizing radiation in double polysilicon bipolar transistor is investigated. The observed differences in the low-frequency noise spectra of devices with different stressing conditions could be interpreted as the differences in the defects-related noise contributions. Low-frequency noise and electrical performance degradation results show that Auger hot carriers greatly induce the atomic hydrogen depassivating the dangling bonds in grain boundaries of emitter polysilicon. However, ionizing radiation damage occurs both at SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> /Si interfaces and in the oxide layer. 1/f noise characteristics indicate that these two damages have different time dependences.

Characterization and Modeling of the Polysilicon Emitter Contact for Circuit Simulation

The emitter contact in bipolar transistors with polysilicon emitters has been characterized based on an improved open-collector (OC) method, which allows extraction of the nonlinear I-V characteristics of the resistance presented by the poly-/monocrystalline emitter interface. The nonlinear characteristics of the interfacial polysilicon-emitter resistance at low currents are modeled using an approximate rectangular-barrier tunnel junction model to extract an upperbound estimate for the thickness of the oxide layer at the poly-/monocrystalline contact. Having verified that the extracted data based on the improved OC method are consistent with the first-principles rectangular tunnel junction model, a data-driven model accounting for the bias-dependence of the emitter series resistance is presented, which employs a voltage-controlled resistor (VCR) to enable the efficient simulation of the effect of the interfacial nonlinearity as well as the substrate bias. SPICE simulations indicate that the VCR-based model for the emitter resistance accurately predicts the measured I-V characteristics obtained using the improved OC method. The utility of a subcircuit-based model explaining the experimentally observable effect of the substrate bias on the behavior of the emitter resistance is also evaluated for circuit simulation.

Temperature Dependent Reliability of Polysilicon Emitter Bipolar Transistors Under High Current Stress

Temperature dependent high forward current stress induced drift of electrical parameters (current gain ( ${\beta }$ ) variations, emitter resistance ( R $_{E}$ ) decrease) in polysilicon emitter bipolar transistors has been revealed. It shows that the ambient temperature surrounding the test device, i.e., the lattice temperature, plays a key role in the reliability issues of the polysilicon emitter bipolar junction transistors under high forward current stress. However, both results from technology computer-aided design (TCAD) simulation and experimental test indicate that the junction temperature only rise up to a certain extent but not very high, i.e., the widely reported self-heating effect is not the essential reason for the device damage in the case of double-polysilicon self-aligned NPN bipolar junction transistor.

CJFET Differential Pairs’ Constructions and Characteristics for Design of Cbicjfet Differential Amplifiers and Differential Difference Amplifiers’

We have developed technology and construction solutions system to increase differential pairs (DP) of JFet with p- and n-channels identity, which are included into silicon complementary bipolar process of SPE “Pulsar” (Moscow). The possibility of creating several types of JFet DPs within the process is shown. The paper presents the results of experimental studies of two types of DP JFet designs with p- and n-channels for the spread of gate-source voltage ΔVGS depending on the drain current and drain-source voltage. The main features of the first design of p-channel JFets were the following: formation of drain/source area due to passive base of npn-transistor and deep collector areas for pnp-transistor; channel formation based on p-layer collector of pnp-transistor; formation of bottom gate using p+ buried layer; top gate formation due to active base and polysilicon emitter of npn-transistor. A feature of the second JFet design was top gate formation due to passive base. The designs of the first and second types of n-channel Jfet were formed similarly, taking into account the replacement of the applied areas of bipolar transistors with opposite ones in the type of conductivity. It was found that with increasing drain current ΔVGS decreases, and with increasing drain-source voltage ΔVGS at high currents increases for DP based on p-channel JFet with the first type of design. The maximum difference ΔVGS was in the range of 5–80 mV for a given differential pair JFet with a p-channel. On plots for DP p-channel JFet with the second type design a significantly lower voltage spread ΔVGS was shown: for example, for the drain current ID = 50 μA the voltage spread ΔVGS did not exceed 10 mV. In this case the voltage spread ΔVGS practially did not depend on drain-source voltage in contrast to differenctial pair of the first type. The second type JFet n-channel differential pairs like for the DP p-channel JFet provided lower spread values in comparison with the first type design: ΔVGS reached values of 5-20 mV. Moreover, for the design of the second type, a significantly weaker effect of the drain-source voltage on ΔVGS was observed at high current densities. The developed designs of differential pairs based on p- and n-channel JFet are recommended for use in organizing the production of CBiCJFet analog circuits, including operations at low temperatures.

Using a TCAD System to Develop a Manufacturing Route for Complimentary Bipolar Transistors as Part of OD Devices

High-speed broadband analog integrated circuits based on a complimentary bipolar technology are widely used in modern equipment. The speed of these circuits is directly related to the boundary frequency of the transistors used. In this paper, we consider some modern approaches to develop complimentary bipolar technologies that ensure a high performance of the integrated circuits and systems on a chip. With the help of TCAD software, the device-technological modeling of the electronic component base is carried out. A technological route is developed for manufacturing the operational amplifier by a high-speed complimentary technology with a self-compliant emitter–base node, based on two layers of polysilicon. To ensure the self-alignment of the base and emitter polysilicon layers when manufacturing n–p–n and p–n–p transistors, an L-shaped nitride spacer is formed. The lateral insulation of the components is made in the form of narrow vertical slits that are lined with oxide and silicon nitride and filled with polysilicon. The manufacturing route developed allows the n–p–n and p–n–p transistors on a single crystal to reach the boundary frequency of 8–10 GHz at the collector–emitter breakdown voltages of more than 10 V. The problem of the complementarity of bipolar transistors is largely solved. In the future, this will make it possible to create a new class of domestic broadband and high-speed analog and digital integrated circuits, as well as ensure the technological independence of the Russian Federation.

Hot-Carrier-Damage-Induced Current Gain Enhancement (CGE) Effects in SiGe HBTs

We investigate high current stress mechanisms and demonstrate how Auger hot carriers can damage both oxide interfaces and polysilicon regions of the emitter and base. A new current gain enhancement (CGE) effect is proposed, which involves hot-carrier damage to the polysilicon emitter and extrinsic base leading to the degradation of the associated minority carrier mobilities. We demonstrate the different CGE mechanisms in SiGe HBTs under forward and inverse modes of operation. The hot-carrier damage responsible for CGE at high injection is explored in depth with the help of TCAD simulations. Evidence for this effect has been gathered with good statistical significance from various stress conditions, various technologies, complimentary (NPN + PNP) devices, and from dc and ac measurements. The new polysilicon degradation mechanism proposed in this paper has been generalized and is important for accurately modeling the changes in base resistance and current gain (β ) at high injection, where circuits are typically biased to extract maximum device performance.

An Investigation of the Effects of Emitter Pre-Deposition Temperature in Double-Diffued Polysilicon Emitter Bipolar Transistors

An Investigation of the Effects of Emitter Pre-Deposition Temperature in Double-Diffued Polysilicon Emitter Bipolar Transistors

A comprehensive semi-analytical model of the polysilicon emitter contact in bipolar transistors

This paper aims to develop a comprehensive physical model for a bipolar transistor’s polysilicon-contacted emitter. Poisson’s equation is solved numerically in the emitter–base space charge region to specify the boundary conditions and the excess minority carriers injected from base to emitter. The continuity and current transport equations are also solved numerically to obtain the minority carrier current in the emitter region. The polysilicon along with the interface layers is modeled by using an effective value for the lifetime. In this model, all the technological parameters of different emitter regions are taken into consideration. Also, the heavy doping effects and the built-in electric field in the shallow non-homogeneous doped single crystalline layer are also included. Such a systematic model does not exist in the literature. The results of the analytical model are numerically evaluated using MATLAB. The trends provided by the model are validated against published experimental results whenever possible and found to be in good agreement with them.

Reliability Degradation Mechanisms of Horizontal Current Bipolar Transistor

The impact of the reverse-bias emitter-base stress and the mixed-mode stress on horizontal current bipolar transistor (HCBT) reliability characteristics is analyzed. Under the stress conditions, hot carriers are generated and injected toward silicon-oxide interfaces above and below HCBT’s emitter n+ polysilicon region where the traps responsible for the base current and beta ( $\beta $ ) degradations are formed. Different degradation rates of three HCBT structures measured under both stresses suggest various contributions of the top and bottom oxides to total damage. A larger contribution of the top interface under the reverse-bias emitter-base stress and of the bottom interface under the mixed-mode stress is determined. A lower doping concentration in the bottom part of the intrinsic transistor and a shorter emitter polysilicon predeposition oxide etching both reduce the generation of interface traps during stress tests. The time-dependent trap degradation simulations are run on the structures with the realistic doping profiles to explain the measured stress data on various HCBT structures.

Carrier-selective contacts for Si solar cells

Carrier-selective contacts (i.e., minority carrier mirrors) are one of the last remaining obstacles to approaching the theoretical efficiency limit of silicon solar cells. In the 1980s, it was already demonstrated that n-type polysilicon and semi-insulating polycrystalline silicon emitters form carrier-selective emitters which enabled open-circuit voltages (Voc) of up to 720 mV. Albeit promising, to date a polysilicon emitter solar cell having a high fill factor (FF) has not been demonstrated yet. In this work, we report a polysilicon emitter related solar cell achieving both a high Voc = 694 mV and FF = 81%. The passivation mechanism of these so-called tunnel oxide passivated contacts will be outlined and the impact of TCO (transparent conductive oxide) deposition on the injection-dependent lifetime characteristic of the emitter as well as its implications on FF will be discussed. Finally, possible transport paths across the tunnel oxide barrier will be discussed and it will be shown that the passivating oxide layer does not lead to a relevant resistive loss and thus does not limit the solar cell's carrier transport. Contrary to amorphous silicon-based heterojunction solar cells, this structure also shows a good thermal stability and, thus, could be a very appealing option for next generation high-efficiency silicon solar cells.

Lumped Models for Assessment and Optimization of Bipolar Device RF Noise Performance

We present a method for simulation of RF noise characteristics of both intrinsic and complete Si(Ge) heterojunction bipolar transistors (HBT's), aiming at support for device design and optimization. RF noise at the intrinsic device level is addressed through an equivalent circuit based on a discretization of partial differential equations describing the transport of minority carriers in quasi-neutral regions. Effects of nonuniform impurity/bandgap distribution and finite velocity recombination at the polysilicon emitter contact are accounted for. Accuracy is verified against analytical results at intrinsic device level. Assessment of noise characteristics of a complete industrial SiGe HBT demonstrates the practical relevance of nonquasi-static effects on noise characteristics. Exploration of the impact of intrinsic base doping profiles on noise performance demonstrates the potential for device optimization.

(Keynote) History and Future Directions in SiGe HBT BiCMOS Technology and Its Applications

The development of SiGe BiCMOS has mirrored silicon semiconductor development as the technology transitioned from Ge transistors, to silicon transistors, to ion-implanted base, to polysilicon emitter transistors, and finally to SiGe HBTs and SiGe BiCMOS. While the physics of the graded base SiGe HBT transistor was established early on in 1954 by Herb Kroemer it was not until the 1980s that SiGe HBTs were first realized. At the core of the SiGe Heterojunction Bipolar transistor development is the SiGe Epitaxy. In fact the SiGe HBT drove the development of the SiGe:B S/D processes now used for stressors in advanced CMOS since it was the first commercial technology with SiGe layers. SiGe HBT BiCMOS continues to find large volume production opportunities in applications that require mostly RF/Analog and less digital content (Big-A/little-D). Scaling has driven the speed performance ( f MAX ) towards terahertz levels to open up yet more applications. Many challenges still exist in the technology.

Direct Parameter Extraction Of Base and Emitter Resistances For SiGe HBTs Using DC Data Only

A new method to directly extract base and emitter resistance parameters for SiGe HBTs using the Mextram bipolar compact transistor model has been presented. The method only requires a standard forward Gummel measurement and accounts for several second order effects like high-injection base conductivity modulation, Early effect and emitter current crowding. Base and emitter resistance parameters have been extracted over a wide temperature range (300K - 93K) for a first generation 0.5µm SiGe HBT with a peak cut-off frequency of 50 GHz at 300K. The HBT features a heavily doped poly-silicon emitter, an extrinsic base region doped well above the Mott's transition (3e18 cc for boron in silicon) and an intrinsic base region doped very close to the Mott's transition. The extracted parameters have been verified by comparison with several different methods.

Design considerations for integration of Horizontal Current Bipolar Transistor (HCBT) with 0.18 μm bulk CMOS technology

Design issues associated with integration of Horizontal Current Bipolar Transistor (HCBT) with 0.18 μm bulk CMOS process are examined and the effects of fabrication parameters on transistor performance analyzed. HCBT is fabricated on a sidewall of a silicon hill defined by shallow trench isolation (STI). Height of the transistor is limited by the STI depth of 350 nm. Impact of vertical and horizontal dimensions on electrical performance of the transistor are analyzed by simulations with emphasis on extrinsic base design. Base current is reduced by high extrinsic base concentration and increased link-base length. Current gain is increased from 16 to 67 for transistor processed with the optimized extrinsic base profile. High-frequency performance is degraded by the collector charge sharing effect and can be improved by the larger separation between the extrinsic base and emitter, which is achieved with a small thickness of emitter polysilicon region. Misalignment tolerances of the extrinsic base implantation mask show no great impact on transistor’s AC performance.

Discussions and extension of van Vliet’s noise model for high speed bipolar transistors

The general van Vliet noise model for transistors was derived for base minority carriers only under adiabatic boundary conditions. This paper extends the model by including the emitter minority carrier noise and the base–collector space charge region (CB SCR) effects based on the mathematical framework developed by van Vliet. Both the finite surface recombination velocity at polysilicon emitter and the finite carrier exit velocity at CB SCR are considered. It is proved that the van Vliet model can be directly used to include the emitter minority carrier noise, and the model holds when the two finite velocity boundary conditions are imposed. A new set of equations are derived to include the effect of CB SCR delay on noise.

Modelling of parasitic effects induced by electrically active defects in a SiGe HBT

In this paper, we present a numerical modelling of a NPN SiGe heterojunction bipolar transistor (HBT) realized in an industrial 0.35 µm BiCMOS process, using our own software simulator “SIBIDIF”, taking into account some electrically active defects in the HBT device. The electric performances of this device can be penalized by the presence of defects inherent to the complex structure shrinking. For our devices, most of these relevant defects are located at the vertical interface between the spacers and the polysilicon emitter, due to the Reactive Ion Etching (RIE) process step. Nevertheless, their localization, as well as theirs effective density or their capture section, have an influence on the electric characteristics of the HBT's. As a check, we find some good agreement between our simulated results and some experimental ones. Our work is focused on the identification of defects responsible for the current fluctuations at the origin of low frequency noise or Random Telegraphic Signals in industrial submicronic BiCMOS technologies. Gummel characteristics are simulated in order to identify generation-recombination or trap assisted tunnelling process in the base current. We have shown that devices having an excess base current present random discrete fluctuations on the base current.

Simple analytical solution and efficiency improvement of polysilicon emitter solar cells

A simple analytical model has been developed to simulate the performance of solar cells with polysilicon contact on the front surface. The polysilicon layer with a columnar grain structure is modeled by an effective recombination velocity using a two-dimensional transport equation. A one-dimensional transport equation in the single-crystal emitter is solved, taking into account bulk recombination and non-uniformly doped emitter. Then, simple analytical expressions for the emitter reverse saturation current and light-generated current densities are obtained. The collection of the light-generated carriers in polysilicon layer has been discussed and an analytical solution of the light-generated current is derived. The results show that the polysilicon layer can result in a decrease in emitter reverse saturation current density and an increase in solar cell photovoltaic parameters. In fact, the emitter region should not be treated as a ‘dead layer’ because thin polysilicon layer front surface contact gives an improvement of about 60 mV for the open-circuit voltage, 3.6 mA/cm 2 for the photocurrent, and 3.9% for the cell efficiency.

Properties and benefits of fluorine in silicon and silicon-germanium devices

This paper reviews the behaviour of fluorine in silicon and silicon-germanium devices. Fluorine is shown to have many beneficial effects in polysilicon emitter bipolar transistors, including higher values of gain, lower emitter resistance, lower 1/f noise and more ideal base characteristics. These results are explained by passivation of trapping states at the polysilicon/silicon interface and accelerated break-up of the interfacial oxide layer. Fluorine is also shown to be extremely effective at suppressing the diffusion of boron, completely suppressing boron transient enhanced diffusion and significantly reducing boron thermal diffusion. The boron thermal diffusion suppression correlates with the appearance of a fluorine peak on the SIMS profile at approximately half the projected range of the fluorine implant, which is attributed to vacancy- fluorine clusters. When applied to bipolar technology, fluorine implantation leads to a record fT of 110 GHz in a silicon bipolar transistor.