Polysilicon Emitter Research Articles

Design and optimization of a buried channel PMOS integrable in a Si 1− xGe x BiCMOS process

A strained Si 1− x Ge x -channel PMOSFET, fully integrable in a standard Si 1− x Ge x BiCMOS process is proposed. It uses an n +-polysilicon emitter of the bipolar transistor as the gate, and has a p-type Si 1− x Ge x channel, making it a truly buried channel device. It uses only two extra masks and a few minor changes in the baseline BiCMOS flow, keeping the additional processing cost low. The basic device design is systematically optimized to get the best compromise among hole confinement in Si 1− x Ge x , layer stability and channel hole mobility. Optimization was done using Ge fraction dependent process and device simulation parameters for the first time. A novel, semi-analytical approach to model the effect of Ge fraction on hole current was used. The impacts of Si cap layer thickness, Si 1− x Ge x film thickness, channel doping and Ge fraction were investigated. During process and device design, care was taken to ensure that the Si 1− x Ge x layer remains strained as well as the standard available devices are not impacted by additional process steps. The optimized device shows a 2× gain in transconductance and in drain current over the standard PMOS device available in the baseline process.

Effects of<tex>$hboxH_2$</tex>Annealing and Polysilicon Emitter Structure on<tex>$hboxH_FE$</tex>of n–p–n Bipolar Junction Transistors

This paper presents the effects of H/sub 2/ annealing and polysilicon emitter structures on H/sub FE/ characteristics of n-p-n bipolar junction transistors. The increase of the number of H/sub 2/ annealing steps results in the device performance (H/sub FE//spl times/V/sub A/) improvement by 27.8%, due to the formation of H-Si dangling bonds, which allow the decrease of the base current. In addition, the bilayer of undoped polysilicon deposition/ion implantation and in situ doped polysilicon in the ploy emitters greatly improve the level of H/sub FE/ reliability and 1/f noise characteristic. The experimental results of H-Si dangling bond property at the polysilicon grain boundaries and polysilicon interface with the H/sub 2/ annealing steps in n-p-n bipolar junction transistor formulation will be also presented.

As-doped polysilicon emitters with interfacial oxides and correlation to bipolar device characteristics

A detailed investigation of in situ-doped polysilicon emitters with interfacial oxide employed in implanted-base Si bipolar junction and epitaxial-base silicon/germanium (SiGe) heterojunction bipolar transistors is presented. In order to tune and control transistor parameters such as current amplification we modify the poly/monocrystalline silicon interface sandwiched between the emitter polysilicon and the base substrate or epitaxy. Various types of interface oxidation were examined and correlated to bipolar device data. We profoundly studied subnanometer silicon oxide growth by rapid thermal oxidation, low-pressure furnace oxidation, and chemical oxidation. Also a combination of thin chemically grown oxides with a thermal postoxidation was characterized. We correlate the oxide thickness to transistor parameters such as current amplification β. Also, the influence of As-enhanced oxide breakup during different emitter anneals as well as the dependence on annealing parameters on β was studied.

Visualizing the Doping Profile of a Silicon Germanium HBT With Polysilicon Emitter Using Electron Holography

Modern bipolar transistors use polysilicon emitters and an epitaxial grown silicon germanium (SiGe) base. For device optimization, both the SiGe base and the region of the diffused emitter is of special interest. In this paper, electron holography is applied to visualize and directly measure the two-dimensional distribution of the local potential in a high-performance SiGe heterojunction bipolar transistor. Special emphasis is put on investigating the region of the emitter diffused into the epitaxially grown base layer. In addition, we investigate the self-aligned base-link construction. We compare electron holographic measurements of the whole transistor to secondary ion mass spectrometric (SIMS) data and discuss the results.

Improvement of porous polysilicon nano-structured emitter for vacuum packaged devices

Porous polysilicon (PPS) emitters were fabricated by depositing an Au thin film on a thermally oxidized polysilicon and their emission properties were examined. The emission properties were also measured for the emitters with various Au thicknesses and the vacuum packaged devices were then developed. The experimental results show that the electrical performances of PPS emitters decreased, because high-temperature packaging process will lead to thermally induced phenomenon between thin layers. We have carried out optimal-thickness variation in Au thickness to improve electron emission properties of PPS emitters packaged. When PPS emitters packaged was driven directly, the field-induced electron emission through anode phosphor was observed.

Effect of Interfacial Oxide Thickness on 1/f Noise in Polysilicon Emitter BJTs

The role of the interfacial oxide (IFO) between the polysilicon and monosilicon emitter regions on the noise behavior of n-p-n poly-emitter bipolar transistors was investigated through 1/f noise measurements. Bipolar junction transistors with different IFO thickness, and emitter geometry were utilized. Measurements with variable external base bias resistance (R/sub S/) were used to investigate the relative contribution of each individual noise source from the base current (S/sub IB/), the collector current (S/sub IC/) and, the internal emitter and base series resistances (S/sub Vr/). When the voltage noise power spectral densities S/sub VC/ and S/sub VB/ were measured across resistances in series with the collector and base, respectively, using a relatively large R/sub S/ (/spl sim/1 M/spl Omega/), S/sub IB/ was found to have the dominant noise contribution at lower bias currents. On the other hand, when the voltage noise power spectral densities S/sub VC/ and S/sub VE/ were measured across resistances in series with the collector and emitter, respectively, in a different experimental setup with a low R/sub S/ value, S/sub Vr/ was found to have the dominant noise contribution at higher bias currents. IFO was found to increase S/sub IB/, S/sub IC/, and S/sub Vr/. S/sub IB/ was modeled as a combination of tunneling and diffusion fluctuations of the minority carriers in the emitter; whereas S/sub IC/ was modeled as a combination of number and diffusion fluctuations of the minority carriers in the base. S/sub Vr/ was attributed to the internal emitter resistance noise originating from the fluctuation in the majority carrier flow through the IFO.

Review of low-frequency noise behaviour of polysilicon emitter bipolar junction transistors

For many analogue integrated circuit applications, the polysilicon emitter bipolar junction transistor (PE-BJT) is still the preferred choice because of its higher operational frequency and lower noise performance characteristics compared to MOS transistors of similar active areas and at similar biasing currents. The authors briefly review why bipolar transistors are still of great interest and in widespread use in analogue integrated circuits. The review includes a comparison between BJTs and MOSFETs using a simple small-signal equivalent circuit with important parameters that can be used to compare these two technologies. An extensive review of the popular theories used to explain low-frequency noise results is presented. However, in almost all instances, these theories have not been fully tested. After a review of the effects of different processing technologies and conditions on the noise performance of PE-BJTs, a summary of some of the key technological steps and device parameters and their effects on noise is presented. The effects of temperature and emitter geometries scaling is reviewed. It is shown that dispersion of the low-frequency noise in ultrasmall geometries is a serious issue since the rate of increase of the noise dispersion is faster than that of the noise itself as the emitter geometry is scaled to smaller values. The same effect, but to a greater extent, is also observed in MOSFETs. Finally, some ideas for future research on PE-BJTs, some of which are also applicable to SiGe or SiGeC heterojunction bipolar transistors and MOSFETs, are presented after the conclusions.

An equivalent heterojunction-like model for polysilicon emitter bipolar transistor

A new method was presented in this article to explain high current gain of polysilicon emitter transistor. By regarding interfacial oxide between polysilicon emitter and silicon emitter as a wide band gap material which can limit minority transport from silicon to polysilicon, thus improve emitter injection efficiency and increase current gain, the characteristics of RCA transistor (a ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) can be explained expediently. The theory also applied to HF transistor by treating difference band gap Δ E g between interfacial material and silicon as zero. Comparison between experimental and theoretical results was made and they are accordant. Through equivalent model Δ E g of a RCA transistor can be estimated as 101 meV.

Polycrystalline silicon-germanium emitters for gain control, with application to SiGe HBTs

This paper investigates germanium incorporation into polysilicon emitters for gain control in SiGe heterojunction bipolar transistors. A theory for the base current of a polySiGe emitter is developed, which combines the effects of the polySiGe grains, the grain boundaries and the interfacial layer at the polySiGe/Si interface into an expression for the effective surface recombination velocity of a polySiGe emitter. Silicon bipolar transistors are fabricated with 0, 10 and 19% Ge in the polySiGe emitter and the variation of base current with Ge content is characterized. The measured base current for a polySiGe emitter increases by a factor of 3.2 for 10% Ge and 4.0 for 19% Ge compared with a control transistor containing no germanium. These values are in good agreement with the theoretical predictions. The competing mechanisms of base current increase by Ge incorporation into the polysilicon and base current decrease due to an interfacial oxide layer are investigated.

Minority carrier transport equation for bipolar transistors with polysilicon emitter contact

In order to improve the current gain via a reduction of the emitter base junction saturation current density, a perpendicular ordering of the grain boundaries (columnar grain boundaries) in the polysilicon emitter-region of a bipolar transistor is proposed. The complex polysilicon current component is obtained by a two-dimensional resolution of the current transport equation along the polysilicon region. The minority carrier current density component in the non-uniformly heavily doped single-crystal emitter is calculated by an average value approach. The influence of the two-dimensional structure of the polysilicon region on the current gain is analysed, and it is shown that the current gain decreases with increasing grain number. The evolution of the normalised current gain in terms of physical parameters is studied. The results show that the current gain improves with polysilicon thickness for a thin oxide layer, while it is insensitive for a thick oxide layer. In addition, the results show that the bulk recombination in a single-crystal emitter cannot be neglected in devices with a deliberately grown interfacial oxide.

Electrical behavior of field-emission device with C-based surface layer

Lateral type poly-silicon field emitters were fabricated by utilizing the local oxidation of silicon process. For the realistic implementation of an ideal field-emission device with quasizero tunneling barrier, a new and fundamental approach has been conducted by inducing a carbon-based ultrathin layer on the cathode tip surface via a field-assisted self-aligning of carbon process. Fundamental lowering of the turn-on field for the electron emission was feasible with the control of both the tip shape and surface barrier height. With the formation of surface carbon layer, a required voltage for an emission current of 10 nA was gradually reduced from ∼60 to ∼0.6 V.

Germanium diffusion in polysilicon emitters of SiGe heterojunction bipolar transistors fabricated by germanium implantation

A study is made of germanium diffusion in polysilicon emitters of SiGe heterojunction bipolar transistors made by germanium implantation. Implanted Ge is found to diffuse from the single-crystal silicon substrate into deposited polysilicon emitter layers during rapid thermal anneal at 1045 °C. Measurements of germanium diffusivity in polycrystalline silicon are reported at temperatures between 800 and 900 °C and modeled by an Arrhenius relationship with a preexponential factor of Do=0.026±0.023 cm2/s and an activation energy of E=2.59±0.36 eV. The measured diffusivity in polycrystalline silicon is ≈104 times larger than that reported for single-crystal silicon. It is hypothesised that germanium diffusion in polysilicon occurs by diffusion along grain boundaries.

Improvement of RCA transistor using RTA annealing after the formation of interfacial oxide

A polysilicon emitter RCA transistor (an ultra-thin interfacial oxide layer exists between polysilicon and silicon emitter) is presented which can operate at 77 K for the first time. An ultra-thin (1.5 nm) interfacial oxide layer is grown deliberately between polysilicon and silicon emitter using RCA oxidation and excellent device stability is obtained after rapid thermal annealing (RTA) treatment in nitrogen atmosphere. The RCA transistor exhibits good electrical performance at very low temperature for an emitter area of 3 /spl times/ 8 /spl mu/m/sup 2/. The maximum toggle frequency of a 1:2 static divider is 1.2 GHz and 732 MHz at 300 K and 77 K, respectively.

P‐44: Optimization and Characterization of the Porous Poly‐silicon Emitter

AbstractIt is estimated that a porous polysilicon (PPS) diode with a structure of Au/PPS/n‐type Si operates as an efficient stable surface emitting cold cathode. 2.0 μm of an nondoped polysilicon layer is formed on an heavily doped n‐type silicon wafer and anodized in a solution of HF(50%): ethanol = 1: 1 under illumination by a 500 W tungsten lamp from a distance of 20 cm. The electron emission properties of the PPS diode were investigated as a function of anodizing condition. It was found that the electron emission properties depend on the anodizing condition, and the optimum anodizing condition is 10mA/cm2 for 15 seconds. The PPS diode emitter fabricated by using the optimum condition has higher efficiency, lower diode current and higher emission current compared to that of other PPS diode emitter. The electron emission characteristics as a function of ambient pressure and the electron trajectory were also studied. Furthermore, the fluctuation properties of the PPSE was investigated and discussed.

Optimization of a 0.6 μm, single polysilicon emitter bipolar technology versus narrow emitter effects

A novel 0.6μm, single polysilicon emitter bipolar technology has been optimized in order to reduce the consequences of narrow emitter effects (NEE) appearing at the laterals of the emitter area. The primary technological mechanisms of these effects have been studied and differentiated for this technology. They have been found to be the polysilicon over-etch into the underlying silicon, the pedestal oxidation, both of them in the area of the extrinsic base implantation, and the extrinsic base lateral diffusion. Designs of experiments techniques have been used in order to study all these technological elements and their effect on the final performance of the transistors. Common emitter current gain variation versus emitter width has been studied by means of test structures and an optimization method is proposed. Lateral diffusion of extrinsic base has been identified as main source of NEE in this technology, which reduces the transistors current gain. Pedestal oxidation has been identified as secondary source of these effects, acting in an opposite way of lateral diffusion increasing the transistors current gain. This opposed effects have been tuned in the technological optimization to minimize the NEE by means of a mutual compensation.

A new model for the low-frequency noise and the noise level variation in polysilicon emitter BJTs

Presents a new, physically-based model for the low-frequency noise in high-speed polysilicon emitter bipolar junction transistors (BJTs). Evidence of the low-frequency noise originating mainly from a superposition of generation-recombination (g-r) centers is presented. Measurements of the equivalent input noise spectral density (SIB) showed that for BJTs with large emitter areas (AE) S(I/sub B/) is proportional to 1/f, as expected. In contrast, the noise spectrum for BJTs with submicron A/sub E/ showed a strong variation from a 1/f-dependence, due to the presence of several g-r centers. However, the average spectrum has a frequency dependence proportional to 1/f for BJTs with large as well as small A/sub E/. The proposed model, based only on superposition of g-r centers, can predict the frequency-, current-, area-, and variation-dependency of with excellent agreement to the measured results.

Low-frequency noise in polysilicon-emitter bipolar transistors

The authors present a review of low-frequency noise (LFN) in polysilicon-emitter (PE) bipolar junction transistors (BJTs). It includes noise results from unstressed as well as stressed devices. A discussion of the possible physical origins of low-frequency noise is presented. Details of noise measurement and a simple noise equivalent circuit, with related noise spectral-density expressions, are given. The first part of the paper deals with noise in virgin or unstressed devices. It starts with a detailed discussion of low-frequency noise results in virgin devices. This includes noise in ultra-small transistors and a discussion of the possible physical origin(s) of the noise. Low-frequency noise in npn and pnp transistors and a technique to estimate the collector 1/f noise are then presented. Since devices are scaled to achieve better high-frequency performance, a discussion of low-frequency noise as a function of emitter geometry for transistors from several different technologies is presented. The second part of the paper deals with degradation of the LFN performance due to electrical stress. It begins with a discussion of degradation mechanisms, followed by a phenomenological discussion of low-frequency noise after hot-carrier (HC) stress. A discussion of the modelling of low-frequency noise after hot-carrier degradation due to reverse current or reverse bias voltage stresses is presented. The effects of forward bias degradation on the low-frequency noise in BJTs are presented and discussed. Finally, it is demonstrated that the noise in PE-BJTs is more sensitive to degradation than the DC characteristics.

Polysilicon: a versatile material for microsystems

The initial attraction of polysilicon was the ability to deposit semiconductor layers on a wide range of substrates. This leads to the development of polysilicon gate MOS, polysilicon emitters and a range of passive devices. In the field of sensors and actuators, the strain sensors, based on piezoresistive effect, was one of the first successful applications. However, it was probably the development of surface micromachining, which received the most attention. The ability to deposit polysilicon on oxide meant that free-standing structures could be fabricated and this has lead to a wide range of successful devices. Polysilicon has a structure comprising small single-crystal grains with many orientations separated by thin grain boundaries. The size of these grains is highly dependent upon processing and therefore a wide range of electrical and mechanical properties can be achieved. This yields greater flexibility but this sensitivity to process parameters can lead to problems in obtaining a stable process. This paper will look back at the development of polysilicon, its structure, fabrication and both mechanical and electrical properties.

A REVIEW OF 1/f NOISE IN TERMS OF MOBILITY FLUCTUATIONS AND WHITE NOISE IN MODERN SUBMICRON BIPOLAR TRANSISTORS — BJTs AND HBTs

Experimental studies on low frequency noise in bipolar junction transistors (BJT) including polysilicon emitter, hetero-junction bipolar transistors (HBTs) and silicon-germanium hetero-junction transistors (SiGe HBTs) are reviewed. The 1/f noise is treated in terms of mobility fluctuations. The validity of a new empirical relation between the 1/f noise corner frequency fc (the frequency where the 1/f noise and shot noise are equal) and the peak cutoff frequency frpeak is investigated. The experimental procedure to investigate the most dominant low-frequency noise source in the equivalent circuit is described. At medium frequencies, the white noise becomes dominant and the noise figure is calculated taking into account the emitter and base series resistance.

The Effect of Device Parameters on the Emitter Transit Time of a PET

Polysilicon Emitter Transistors (PETs) which are now being widely used in high speed bipolar circuits because of their extremely low emitter transit time τE, have broken-up interfacial oxide layer due to annealing process which they undergo. The effect of oxide layer break-up at the mono-poly interface of the emitter region of a PET on τE is studied here. The effect of doping profile, peak doping concentration, thickness of interfacial oxide layer on τE is studied also. Exponential doping distribution alongwith concentration dependent bandgap narrowing effect and concentration dependent diffusion constant in the monosilicon emitter region are considered.