Emitter-coupled Logic Research Articles

InGaAs-InP DHBTs for increased digital IC bandwidth having a 391-GHz f/sub /spl tau// and 505-GHz f/sub max/

InP-In/sub 0.53/Ga/sub 0.47/As-InP double heterojunction bipolar transistors (DHBT) have been designed for use in high bandwidth digital and analog circuits, and fabricated using a conventional mesa structure. These devices exhibit a maximum 391-GHz f/sub /spl tau// and 505-GHz f/sub max/, which is the highest f/sub /spl tau// reported for an InP DHBT-as well as the highest simultaneous f/sub /spl tau// and f/sub max/ for any mesa HBT. The devices have been aggressively scaled laterally for reduced base-collector capacitance C/sub cb/. In addition, the base sheet resistance /spl rho//sub s/ along with the base and emitter contact resistivities /spl rho//sub c/ have been lowered. The dc current gain /spl beta/ is /spl ap/36 and V/sub BR,CEO/=5.1 V. The devices reported here employ a 30-nm highly doped InGaAs base, and a 150-nm collector containing an InGaAs-InAlAs superlattice grade at the base-collector junction. From this device design we also report a 142-GHz static frequency divider (a digital figure of merit for a device technology) fabricated on the same wafer. The divider operation is fully static, operating from f/sub clk/=3 to 142.0 GHz while dissipating /spl ap/800 mW of power in the circuit core. The circuit employs single-buffered emitter coupled logic (ECL) and inductive peaking. A microstrip wiring environment is employed for high interconnect density, and to minimize loss and impedance mismatch at frequencies >100 GHz.

A burst-mode receiver for 1.25-Gb/s ethernet PON with AGC and internally created reset signal

This paper presents a burst-mode receiver for 1.25-Gb/s Ethernet PON system using mixed-mode CMOS 0.18-/spl mu/m technology. With the modified cell-based AGC function and differential feed-forward topology, the receiver achieves sensitivity of -26.4 dBm, overload of -5.4 dBm, and a loud/soft ratio of 21 dB while keeping the low-voltage positive emitter-coupled logic (LVPECL) differential output level fully compliant with the ethernet passive optical network (EPON) standard. Unlike other burst-mode receivers, the design obtains fast response even without a reset signal from the network layer by creating a reset signal internally based on the incoming signal. This setting allows for simple system design. The overall architecture and several blocks are optimized in accordance with internal reset creation. Minimum guard time and preamble time are 250 and 50 ns, respectively; all timing parameters are better than the current EPON standard. The prototype contains all components on-chip that occupies 0.9/spl times/1.9 mm/sup 2/ and consumes 160 mA current from a 3.3-V supply.

Self-Aligned InP DHBT with<tex>$f_tau$</tex>and<tex>$f_max$</tex>Over 300 GHz in a New Manufacturable Technology

We report self-aligned indium-phosphide double-heterojunction bipolar transistor devices in a new manufacturable technology with both cutoff frequency (f/sub /spl tau//) and maximum oscillation frequency (f/sub max/) over 300 GHz and open-base breakdown voltage (BV/sub ceo/) over 4 V. Logic circuits fabricated using these devices in a production integrated-circuit process achieved a current-mode logic ring-oscillator gate delay of 1.95 ps and an emitter-coupled logic static-divider frequency of 152 GHz, both of which closely matched model-based circuit simulations.

Low swing differential logic for mixed signal applications

Low swing differential logic operated at a constant bias current is a promising approach to reduce the switching noise in sensitive mixed mode circuits. Most differential logic families do not allow a significant change in bias current between cells so that it is difficult to optimize the power consumption for a required speed. A nonlinear load circuit for differential current-steering logic consisting of a current source in parallel with a diode connected FET is therefore proposed. The logic levels can be easily adjusted with an external supply voltage so that the circuit design is significantly simplified. As an example application a counter for the use in pixel readout chips is presented. The layout area using radiation hard design rules is not significantly larger than CMOS. The logic can be operated at very low power.

High-speed scaled-down self-aligned SEG SiGe HBTs

A scaled-down self-aligned selective-epitaxial-growth (SEG) SiGe HBT, structurally optimized for an emitter scaled down toward 100 nm, was developed. This SiGe HBT features a funnel-shaped emitter electrode and a narrow separation between the emitter and base electrodes. The first feature is effective for suppressing the increase of the emitter resistance, while the second one reduces the base resistance of the scaled-down emitter. The good current-voltage performance - a current gain of 500 for the SiGe HBT with an emitter area of 0.11 /spl times/ 0.34 /spl mu/m and V/sub BE/ standard deviation of less than 0.8 mV for emitter width down to about 0.13 /spl mu/m - demonstrates the applicability of this SiGe HBT with a narrow emitter. This SiGe HBT demonstrated high-speed operation: an emitter-coupled logic (ECL) gate delay of 4.8 ps and a maximum operating frequency of 81 GHz for a static frequency divider.

4-bit multiplexer/demultiplexer chip set for 40-gbit/s optical communication systems

We have designed and fabricated a low-power 4:1 multiplexer (MUX), 1:4 demultiplexer (DEMUX) and full-clock-rate 1:4 DEMUX with a clock and data recovery (CDR) circuit using undoped-emitter InP-InGaAs HBTs. Our HBTs exhibit an f/sub T/ of approximately 150 GHz and an f/sub max/ of approximately 200 GHz at a collector current density of 50 kA/spl mu/m/sup 2/. In the circuit design, we utilize emitter-coupled logic and current-mode logic series gate flip-flops and optimized the collector current density of each transistor to achieve low-power operation at required high bit rates. Error-free operation at bit rates of up to 50 Gbit/s were confirmed for the 4:1 MUX and 1:4 DEMUX, which dissipates 2.3 and 2.5 W, respectively. In addition, the full-clock-rate 1:4 DEMUX with the CDR achieved 40-Gbit/s error-free operation.

3.21 ps ECL gate using InP/InGaAs DHBT technology

A new circuit configuration for an emitter-coupled logic (ECL) gate that can reduce propagation delay time has been demonstrated. Nineteen-stage ring oscillators were fabricated using InP/InGaAs double-heterojunction bipolar transistors (DHBTs) with cutoff frequency fT and maximum oscillation frequency fmax of about 232 and 360 GHz, respectively, to evaluate the speed performance of the proposed ECL gate. The minimum propagation delay is 3.21 ps/gate. The proposed ECL gate is about 8% faster than the conventional ECL gate.

Synchronisation of a femtosecond laser and a Q-switched laser to within 50 ps

A Nd:YLF laser emitting 2-ns pulses synchronised with a femtosecond Cr:forsterite laser is built. The pulse duration and synchronisation are ensured by two Pockels cells, in which voltage pulses are synchronised with the femtosecond laser by fast emitter-coupled logic elements. One of the Pockels cells ensures Q-switching, while the other cuts a short pulse from a 15-ns Q-switched pulse. The experimental results show that the two-step scheme proposed for synchronisation of a Q-switched laser and a passively mode-locked laser provides quite simple and reliable synchronisation of these lasers with a jitter of a few tens of picoseconds.

Preface: Packaging

In 1993, IBM began replacing bipolar emitter-coupled logic (ECL) in its large mainframe computers with complementary metal-oxide semiconductor (CMOS) logic because of the very high integration density of CMOS, its high switching speed, lower switching current, and excellent reliability. Advances in CMOS microprocessor technology have had a spillover effect on packaging technology. The increased functionality and density of CMOS-based control chips, along with the use of surface-mount technology, have resulted in the denser packaging required to support multichip modules (MCMs).

A 32-word by 32-bit three-port bipolar register file implemented using a SiGe HBT BiCMOS technology

Describes a novel system level design for a 32-word by 32-bit bipolar register file with two read ports and one write port. The register file is implemented using a SiGe HBT BiCMOS technology and emitter-coupled logic (ECL)-style circuits. It has dimensions of 1.0 mm by 1.8 mm. The read access time for the register Me is between 340 and 350 ps using read port A, while the read access time using read port B is between 360 and 380 ps. Read access times as low as 290 ps were measured for some columns, however. The write access time for the register file is between 250 and 340 ps, using a write enable pulse with a width between 130 and 170 ps. The estimated register file power dissipation is 4.7 W using a 4.5-V supply.

SEE analysis of digital InP-based HBT circuits at gigahertz frequencies

A device/circuit simulation is used to analyze a gigahertz clocked emitter-coupled logic circuit being perturbed by a single event. Results provide an understanding of charge collection in the heterojunction bipolar transistor. A technique for single-event hardening is demonstrated by simulation.

2-bit adder: carry and sum logic circuits at 19GHz clockfrequency in InAlAs/InGaAs HBT technology

Carry and sum circuits for a 2-bit adder used in a pipelined 2N-bit adder-accumulator architecture are reported. To obtain high clock rates in a design with multiple gate delays a novel merged AND-OR-Latch structure using four-level series gated current steering logic is employed. These integrated circuits were fabricated in InAlAs/InGaAs transferred substrate heterojunction bipolar transistor technology and operate up to 19 GHz clock rate.

A 50-GHz static frequency divider and 40-Gb/s MUX/DEMUX using self-aligned selective-epitaxial-growth SiGe HBTs with 8-ps ECL

A static frequency divider with a maximum operating frequency of up to 50 GHz and a multiplexer (MUX) and a demultiplexer (DEMUX) that both operate at 40 Gb/s were developed for future optical-fiber-link systems. These digital circuits were fabricated using ultra-high-speed self-aligned selective-epitaxial-growth SiGe-base hetero-junction bipolar transistors (HBTs) with self-aligned stacked metal/in-situ doped poly-Si electrodes. These HBTs provide a 95-GHz cutoff frequency, a 108-GHz maximum oscillation frequency, and a minimum emitter-coupled-logic (ECL) gate delay of 8 ps. The excellent results from this digital chipset show that SiGe HBT technology, with its high reliability and cost-effectiveness, will play an important role in future multi-gigabit per second optical-fiber-link systems.

1.2-Gb/s true PECL 100K compatible I/O interface in 0.35-μm CMOS

This paper describes the design and the implementation of input-output (I/O) interface circuits for serial data links in the gigabit-per-second range. The cells were implemented in a 3.3-V 0.35-/spl mu/m CMOS technology in a couple of test chips. The transmitter is fully compatible (DC coupling) with 100K positive emitter-coupled logic (PECL) systems and it is based on the voltage-switching principle in order to allow different termination schemes besides the canonical ECL termination, i.e., 50-/spl Omega/ toward (V/sub DD/-2) V. The addition of some circuit techniques such as dynamic biasing and strobed current switching boosts the dynamic performance of the basic voltage-switching scheme and relaxes the requirements for a high bias current and large-size output devices at the same time. Moreover, thanks to the developed reference circuit, using both feedforward and feedback controls, the output levels are within the 100K tolerance over the full range of process, supply voltage, and temperature (PVT) variations without resorting to external components or on-chip trimming. The receiver cell is based on a complementary-differential architecture providing high speed and low error on the duty cycle of the CMOS output signal. The integrated receiver-transmitter chain exhibits a maximum toggle frequency of 1 GHz, while a chip-to-chip transmission link using the developed I/O interface was tested up to 1.2 Gb/s.

SELF-ALIGNED Si BJT/SiGe HBT TECHNOLOGY AND ITS APPLICATION TO HIGH-SPEED CIRCUITS

In a Si bipolar transistor (BJT) and a SiGe heterojunction bipolar transistor (HBT), self-aligned structures help to improve high-speed and high-frequency characteristics. These structures are used to reduce parasitic capacitance and resistance, and thus maximize the transistor's intrinsic performance. In addition to generally used process technology, selective metal deposition to form electrodes and selective epitaxial growth of Si/SiGe multilayers are applied in the fabrication process. To improve the intrinsic speed, the cutoff frequency, a shallow diffusion process for Si BJTs and a graded-Ge profile SiGe-base layer for SiGe HBTs are used. These also enable a high maximum oscillation frequency and a small gate delay in the emitter-coupled logic through the synergistic effect of the self-aligned structure. Both high-speed digital circuits — frequency dividers up to millimeter-wave bands and a multiplexer/demultiplexer for optical-fiber-links — and high-frequency analog circuits for optical-fiber-links — a preamplifier, an automatic gain control amplifier. a limiting amplifier, and a decision circuit — have been implemented by applying the self-aligned Si BJTs and/or SiGe HBTs.

High-performance implanted base silicon bipolar technology for RF applications

A 0.4 /spl mu/m silicon bipolar technology for mixed digital/analog RF-applications is described. Without increasing the process complexity in comparison to current production technologies transit frequencies of 52 GHz, maximum oscillation frequencies of 65 GHz and minimum noise figures of 0.7 and 1.3 dB at 3 and 6 GHz are achieved. Emitter-coupled logic (ECL) ring oscillators have a minimum gate delay of 12 ps, the low power capability of the technology is proven by a current-mode logic (CML) power delay product of 5.2 fJ and a dynamic frequency divider operates up to 52 GHz. These results demonstrate the suitability of this technology for mobile communications up to at least 6 GHz and for high-speed optical data links at 10 Gbit/s and above.

A 550-ps access 900-MHz 1-Mb ECL-CMOS SRAM

An ultrahigh-speed 1-Mb emitter-coupled logic (ECL)-CMOS SRAM with 550-ps clock-access time, 900-MHz operating frequency, and 12-/spl mu/m/sup 2/ memory cells has been developed using 0.2-/spl mu/m BiCMOS technology. Three key techniques for achieving the ultrahigh speed are a BiCMOS word decoder/driver with an nMOS level-shift circuit, a sense amplifier with a voltage-clamp circuit, and a BiCMOS write circuit with a variable-impedance bitline load. The proposed word decoder/driver and sense amplifier can reduce the delay times of the circuits to 54% and 53% of those of conventional circuits. The BiCMOS write circuit can reduce the power dissipation of the circuit by 74% without sacrificing writing speed. These techniques are especially useful for realizing ultrahigh-spaced high-density SRAMs, which will be used as cache and control memories in mainframe computers.

Self-aligned selective-epitaxial-growth SiGe HBTs: process, device, and ICs

We review the fabrication process and device technologies of a high-speed self-aligned selective-epitaxial-growth (SEG) SiGe-base heterojunction bipolar transistor (HBT), and its potential application in ICs for optical-fiber-link systems. A 0.54-μm-wide SiGe base, self-aligned to the 0.14-μm-wide emitter to reduce collector capacitance, was selectively grown by using a UHV/CVD system. A self-aligned stacked metal/in situ doped poly-Si electrode technology enables low parasitic resistance, and allows the intrinsic base profile to be kept shallow, so it is well-suited to a SiGe-base HBT. A 2-μm-wide insulator refilled trench was introduced to reduce substrate capacitance. This SiGe HBT makes it possible to obtain 95-GHz cutoff frequencies and 97-GHz maximum oscillation frequencies, and ultra-high-speed emitter-coupled-logic (ECL) circuits with an 8-ps gate delay. The technology was applied in ICs required for optical-fiber-link systems, including a 1/8 static frequency divider with a maximum operating frequency of up to 50 GHz, a time-division multiplexer and a demultiplexer operating at 40 Gb/s, a preamplifier with a bandwidth of 35 GHz, an AGC amplifier core with a bandwidth of 32 GHz, and a decision circuit operating at 40 Gb/s.

A 2-GHz clocked AlGaAs/GaAs HBT byte-slice datapath chip

A byte-slice datapath for exploring multi-chip RISC processor development in AlGaAs-GaAs heterojunction bipolar transistor (HBT) technology has been designed, fabricated and tested. The circuits are implemented using differential current-mode logic (CML) and emitter-coupled logic (ECL) with signal swings of 250 mV. Each datapath chip contains a single slice, including an 8-bit by 32-word single-port register file with a 230-ps read access time, and an 8-bit carry-select adder with a 140-ps select path and a 380-ps ripple-carry path. Each unpackaged die was tested using an at-speed boundary scan test scheme. The register file and adder carry chain are also implemented in a special test chip for accurate performance characterization of these critical circuits.

Power reduction techniques for a 1-Mb ECL-CMOS SRAM with an access time of 550 ps and an operating frequency of 900 MHz

This paper describes power reduction circuit techniques in an ultra-high-speed emitter-coupled logic (ECL)-CMOS SRAM. Introduction of a 0.25-/spl mu/m MOS transistor allows a Y decoder and a bit-line driver to be composed of CMOS circuits, resulting in a power reduction of 34%. Moreover, a variable-impedance load has been proposed to reduce cycle time. A 1-Mb ECL-CMOS SRAM was developed by using these circuit techniques and 0.2-/spl mu/m BiCMOS technology. The fabricated SRAM has an ultrafast access time of 550 ps and a high operating frequency of 900 MHz with a power dissipation of 43 W.