Elliptic Curve Crypto Processor Research Articles

Field-programmable gate array (FPGA) hardware design and implementation of a new area efficient elliptic curve crypto-processor

Elliptic curve cryptography provides a widely recognized secure environment for information exchange in resource-constrained embedded system applications, such as Internet-of-Things, wireless sensor networks, and radio frequency identification. As the elliptic-curve cryptography (ECC) arithmetic is computationally very complex, there is a need for dedicated hardware for efficient computation of the ECC algorithm in which scalar point multiplication is the performance bottleneck. In this work, we present an ECC accelerator that computes the scalar point multiplication for the NIST recommended elliptic curves over Galois binary fields by using a polynomial basis. We used the Montgomery algorithm with projective coordinates for the scalar point multiplication. We designed a hybrid finite field multiplier based on the standard Karatsuba and shift-and-add multiplication algorithms that achieve one finite field multiplication in $\frac{m}{2}$ clock cycles for a key-length of m. The proposed design has been modeled in Verilog hardware description language (HDL), functionally verified with simulations, and implemented for field-programmable gate array (FPGA) devices using vendor tools to demonstrate hardware efficiency. Finally, we have integrated the ECC accelerator as an AXI4 peripheral with a synthesizable microprocessor on an FPGA device to create an elliptic curve crypto-processor.

Corrigendum: Throughput/area optimised pipelined architecture for elliptic curve crypto processor

Corrigendum: Throughput/area optimised pipelined architecture for elliptic curve crypto processor

Towards Efficient FPGA Implementation of Elliptic Curve Crypto-Processor for Security in IoT and Embedded Devices

An Elliptic Curve Crypto-Processor (ECCP) is a favorite public-key cryptosystem due to its small key size and its high security arithmetic unit. It is applied in constrained devices which often run on batteries and have limited processing, storage capabilities and low power. This research work presents an effective ECCP architecture for security in IoT and embedded devices. A finite field polynomial multiplier takes the most implementation effort of an ECCP because it is the most consuming operation for time and area. So, the objective is to implement the main operation of Point Multiplication (PM) 𝑄=𝑘𝑃 using FPGA. The aim is to obtain the optimal registers number for an area optimization of ECCP architecture. Moreover, it proposes a time optimization of ECCP based on the liveness analysis and exploiting forward paths. Also, a comparison between sequential and parallel hardware design of PM based on Montgomery ladder algorithm is provided.The developed ECCP design is implemented over Galois Fields GF (2163) and GF (2409) on Xilinx Integrated Synthesizes Environment (ISE) Virtex 6 FPGA. In case of GF (2163), this work achieved an area saving that uses 2083 Flip Flops (FFs), 40876 Lookup Tables (LUTs) and 19824 occupied slices. The execution time is 1.963 s runs at a frequency of 369.529 MHz and consumes 5237.00 mW. In case of GF (2409), this work achieved an area saving that uses 8129 Flip Flops (FFs), 42300 Lookup Tables (LUTs) and 18807 occupied slices. The execution time is 29 s runs at a frequency of 253.770 MHz and consumes 2 W. The obtained results are highly comparable with other state-of-the-art crypto-processor designs. The developed ECCP is applied as a case study of a cryptography protocol in ATMs.

Parallel implementation for ECCP based on Montgomery ladder algorithm

An Elliptic Curve Crypto-Processor (ECCP) is a favourite public-key cryptosystem. It is used for embedded systems due to its small key size and its high security arithmetic unit. It is applied in constrained devices which often run on batteries and have limited processing, storage capabilities and low power. A finite field polynomial multiplier takes the most implementation effort of an ECCP because it is the most consuming operation for time and area. So, it is preferable to optimize this operation especially for light devices where the small area is needed. This research introduces a hardware design for parallel ECCP binary implementation that is based on Montgomery ladder algorithm. This implementation is targeted for GF(2163) and GF(2409) where the executed time are 2.9 μs and 29 μs respectively. The implementation is performed on Xilinx ISE Virtex6.

A Novel Approch for Binary Elliptic Curve Cryptosystem Implementation Over GF(2^409)

Security in embedded systems are presented in this work based on Elliptic Curve crypto-processor (ECCP). Comparison with state-of-the-art algorithms that have been used to implement ECCP are also presented. It proves that Montgomery ladder algorithm is preferred one when the speed is needed. Optimization problem for general ECCP architecture are started from the selected algorithm and ends with liveness analysis and forward path. The inversion operation based on Itoh-Tsujii GF(2409) is discussed in this work. The proposed ECCP is implemented for GF(2163) and GF(2409) where the execution time are 8 μs and 61.2 μs respectively in sequentially design. The design and results are implemented using Xilinx ISE Virtex6.

Throughput/area optimised pipelined architecture for elliptic curve crypto processor

A pipelined architecture is proposed in this work to speed up the point multiplication in elliptic curve cryptography (ECC). This is achieved, at first; by pipelining the arithmetic unit to reduce the critical path delay. Second, by reducing the number of clock cycles (latency), which is achieved through careful scheduling of computations involved in point addition and point doubling. These two factors thus, help in reducing the time for one point multiplication computation. On the other hand, the small area overhead for this design gives a higher throughput/area ratio. Consequently, the proposed architecture is synthesised on different FPGAs to compare with the state-of-the-art. The synthesis results over GF(2 m ) show that the proposed design can work up to a frequency of 369, 357 and 337 MHz when implemented for m = 163, 233 and 283 bit key lengths, respectively, on Virtex-7 FPGA. The corresponding throughput/slice figures are 42.22, 12.37 and 9.45, which outperform existing implementations.

FPGA Implementation of Elliptic Curve Cryptoprocessor for Perceptual Layer of the Internet of Things

FPGA Implementation of Elliptic Curve Cryptoprocessor for Perceptual Layer of the Internet of Things

High-Performance Generic-Point Parallel Scalar Multiplication

A high-performance parallel scalar multiplication method is presented in this paper. The proposed method takes a set of generic points and performs their scalar multiplications in parallel using parallel elliptic curve cryptoprocessors. The method requires neither precomputations nor postcomputations to speed up scalar multiplication and outperforms existing methods. Furthermore, it is scalable and its performance improves as the number of consecutive requests increases. An implementation of the proposed method on an FPGA is presented. The area-time\(^{2}\)\((\hbox {AT}^{2})\) performance metric of the implementation outperforms other recently proposed fast implementations. Accordingly, our method is very attractive for high-speed applications.

Highly Efficient Generic-Point Parallel Scalar Multiplication using Concurrent Precomputations

A B S T R A C T An efficient precomputation-based generic-point parallel scalar multiplication method is presented in this study. The proposed method takes a set of generic points and performs their precomputations concurrently using an equivalent set of elliptic curve cryptoprocessors. Then, parallel scalar multiplications are performed sequentially for each of the generic points. The new method outperforms the existing postcomputation-based methods. Furthermore, it is scalable for any number of parallel processors and performs better as the number of consecutive requests increases. The proposed method has been implemented on an FPGA and its Area-Time 2 (AT 2 ) performance metric outperformed recent fast implementations.

High-performance elliptic curve cryptoprocessors over $$\varvec{GF(2^{m})}$$ G F ( 2 m ) on Koblitz curves

Efficient computation of the finite field arithmetic is required for elliptic curve cryptography over $$G\!F\!(2^{m})$$GF(2m). In order to achieve the above, this paper presents the design of high-performance cryptoprocessors over $$G\!F\!(2^{163})$$GF(2163) and $$G\!F\!(2^{233})$$GF(2233) using finite field multipliers with digit-level processing. The arithmetic operations were implemented in hardware using Gaussian normal bases representation and the scalar point multiplication kP was performed on Koblitz curves using window-$$\tau $$?NAF algorithm with w = 2, 4 and 8. The cryptoprocessors were designed using VHDL description, synthesized on the FPGA Stratix-V using Quartus II 13.0, and verified using ModelSIM and Matlab. The simulation results show that the cryptoprocessors present a very good performance using low area. In this case, the processing times for calculating the scalar point multiplication over $$G\!F\!(2^{163})$$GF(2163) and $$G\!F\!(2^{233})$$GF(2233) for w = 2, 4 and 8 were 9.1, 6.7 and 5.1, and 12.9, 9.5 and 6.8 $$\upmu $$μs, respectively.

Space Optimized Multiplier Architecture for Embedded Cryptoprocessor

The finite field modular multiplier is the most critical component in the elliptic curve crypto processor (ECCP) consuming the maximum chip area and contributing the most to the device latency. Modular multiplication, point multiplication, point doubling are few of the critical activities to be carried out by multiplier in ECC algorithm, and should be managed without compromising on security and without burdening space and time complexities. Since the area complexity of the Crypto processor is mainly based on the Modular Multiplier incorporated within the ECC processor, the major contribution of this work includes the replacement of traditional Karatsuba multiplier with the proposed space optimized multiplier inside the processor The complete modular multiplier and the cryptoprocessor module is synthesized and simulated using Xilinx ISE Design suite 14.4 software. Experimental investigation show an improvement in area efficiency of cryptoprocessor, since proposed scheme occupies relatively reduced percentage area of FPGA as compared to the one using traditional Karatsuba multiplier.

Design of elliptic curve cryptoprocessors over GF(2^163) using the Gaussian normal basis

This paper presents an efficient hardware implementation of cryptoprocessors that perform the scalar multiplication kP over a finite field GF(2163) using two digit-level multipliers. The finite field arithmetic operations were implemented using the Gaussian normal basis (GNB) representation, and the scalar multiplication kP was implemented using the Lopez-Dahab algorithm, the 2-non-adjacent form (2-NAF) halve-and-add algorithm and the wNAF method for Koblitz curves. The processors were designed using a VHDL description, synthesized on the Stratix-IV FPGA using Quartus II 12.0 and verified using SignalTAP II and Matlab. The simulation results show that the cryptoprocessors provide a very good performance when performing the scalar multiplication kP. In this case, the computation times of the multiplication kP using the Lopez-Dahab algorithm, 2-NAF halve-and-add algorithm and 16NAF method for Koblitz curves were 13.37 µs, 16.90 µs and 5.05 µs, respectively.

Design of Elliptic Curve Crypto Processor with Modified Karatsuba Multiplier and its Performance Analysis

ECDSA stands for “Elliptic Curve Digital Signature Algorithm”, it’s used to create a digital signature of data (a file for example) in order to allow you to verify its authenticity without compromising its security. This paper presents the architecture of finite field multiplication. The proposed multiplier is hybrid Karatsuba multiplier used in this processor. For multiplicative inverse we choose the Itoh-Tsujii Algorithm(ITA). This work presents the design of high performance elliptic curve crypto processor(ECCP) for an elliptic curve over the finite field GF(2^233). The curve which we choose is the standard curve for the digital signature. The processor is synthesized for Xilinx FPGA.

Elliptic Curve Cryptoprocessor Implementation on a Nano FPGA: Interesting for Resource-Constrained Devices

This paper presents an implementation of an Elliptic Curve Cryptography (ECC) cryptoprocessor on a Nano Field Programmable Gate Array (FPGA), that maybe be interesting for resource-constrained devices that require moderate level of security. Nano FPGAs offer groundbreaking possibilities in power, size, lead-times, operating temperature and cost. To the best of our knowledge, this is the first ECC implementation on Nano FPGAs. The proposed ECC cryptoprocessor was modeled using VHDL and synthesized on Actel IGLOO AGLN250V2-VQFP100 Nano FPGA. The synthesis results show that the targeted Nano FPGA can't exceed the values of m ≤ 11 bits. This is because of the limited number of resources available on Nano FPGAs, which opens a new challenging opportunity for future Nano FPGAs to satisfy the needs of critical portable applications and resource-constrained devices, such as Wireless Sensor Network (WSN).

A low-power and low-energy flexible GF(p) elliptic-curve cryptography processor

We investigate the use of two integer inversion algorithms, a modified Montgomery modulo inverse and a Fermat’s Little Theorem based inversion, in a prime-field affine-coordinate elliptic-curve crypto-processor. To perform this, we present a low-power/energy GF(p) affine-coordinate elliptic-curve cryptography (ECC) processor design with a simplified architecture and complete flexibility in terms of the field and curve parameters. The design can use either of the inversion algorithms. Based on the implementations of this design for 168-, 192-, and 224-bit prime fields using a standard 0.13 μm CMOS technology, we compare the efficiency of the algorithms in terms of power/energy consumption, area, and calculation time. The results show that while the Fermat’s theorem approach is not appropriate for the affine-coordinate ECC processors due to its long computation time, the Montgomery modulo inverse algorithm is a good candidate for low-energy implementations. The results also show that the 168-bit ECC processor based on the Montgomery modulo inverse completes one scalar multiplication in only 0.4 s at a 1 MHz clock frequency consuming only 12.92 μJ, which is lower than the reported values for similar designs.

Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor

Coupled FPGA/ASIC Implementation of Elliptic Curve Crypto-Processor

Generic-point parallel scalar multiplication without precomputations

The first efficient generic-point parallel scalar multiplication method is presented here. The novelty of the proposed method is that the precomputation overhead can be replaced by postcomputations that can be parallelised. This method will be very attractive for use in high-performance end servers that employ parallel elliptic curve cryptoprocessors.

Highly Efficient Elliptic Curve Crypto-Processor with Parallel GF(2m) Field Multipliers

This study presents a high performance GF(2 m ) Elliptic Curve Crypto-processor architecture. The proposed architecture exploits parallelism at the projective coordinate level to perform parallel field multiplications. In the proposed architecture, normal basis representation is used. Comparisons between the Projective, Jacobian and Mixed coordinate systems using sequential and parallel designs are presented. Results show that parallel designs using normal basis gives better area- time complexity (AT 2 ) than sequential designs by 33-252% which leads to a wide range of design tradeoffs. The results also show that mixed coordinate system is the best in both sequential and parallel designs and gives the least number of multiplications levels when using 3 multipliers and the best AT 2 when using only 2 multipliers.