Electro-thermal Simulation Research Articles

Effect of metal foil size on the actuation properties of micro-chip exploding foil initiator

Exploding foil initiator (EFI)is a special kind of actuator that is used to drive the flyer. To realize high-velocity flyer output and low-energy firing, the size of bridge foil and corresponding structures of EFI were studied. Four kinds of micro-chip exploding foil initiators (McEFI) with different bridge foil sizes were prepared in batches using Micro-Electro-Mechanical System technology. Furthermore, the primary characteristics of the four kinds of bridge foils were comparatively performed and discussed, including the electro-thermal simulation, electrical-explosion properties, and flyer velocities capabilities. Most importantly, the velocities of the ParyleneC (PC) flyer were measured by photonic doppler velocimetry, indicating the PC flyer had better velocity capabilities with the reduction of the size of the bridge foil. The firing property of McEFI was validated by initiating HNS-IV pellets, and the critical threshold energy was determined as 0.22 μF/1095 V based on the sensitivity test. This structural change truly implements the popularization of the high-velocity flyer actuator or initiator.

Design for Ultrahigh-Density Vertical Phase Change Memory: Proposal and Numerical Investigation

The integration level is a significant index that can be used to characterize the performance of non-volatile memory devices. This paper proposes innovative design schemes for high-density integrated phase change memory (PCM). In these schemes, diploid and four-fold memory units, which are composed of nano-strip film GST-based memory cells, are employed to replace the memory unit of a conventional vertical PCM array. As the phase transformation process of the phase change material involves the coupling of electrical and thermal processes, an in-house electrothermal coupling simulator is developed to analyze the performance of the proposed memory cells and arrays. In the simulator, a proven mathematical model is used to describe the phase change mechanism, with a finite element approach implemented for numerical calculations. The characteristics of the GST-strip-based memory cell are simulated first and compared with a conventional vertical cell, with a decrease of 32% in the reset current amplitude achieved. Next, the influences of geometric parameters on the characteristics of memory cell are investigated systematically. After this, the electrothermal characteristics of the proposed vertical PCM arrays are simulated and the results indicate that they possess both excellent performance and scalability. At last, the integration densities of the proposed design schemes are compared with the reference array, with a maximum time of 5.94 achieved.

Accurate Electro-Thermal Computational Model Design and Validation for Inverters of Automotive Electric Drivetrain Applications

This paper proposes the fast and accurate electro-thermal model of the existing Simrod three-phase inverter for an electric vehicle (EV) application. The research focuses on analytical and dynamic electro-thermal models of inverters that can be applied for multi-applications. The optimal design approach of passive filters is presented for the DC and AC sides of the inverter. The analytical model has been established, including a mathematical representation of the inverter and induction motor (IM). The high-fidelity electro-thermal simulation model of an inverter with integrated power loss and thermal model is established. The state-space thermal model (for the IRFS4115PbF device) has been created and incorporated into the MATLAB simulation. The simulation model is then validated with the PLECS software-based thermal model to confirm the accuracy. Indirect field-oriented control (IFOC) is designed for squirrel-cage IM at a maximum power rating of 45 kW and implemented on MATLAB/Simulink. The comparative analysis between the real and simulated results is performed to validate the simulation model at a specific speed, torque, and current. Furthermore, the electro-thermal simulation model has been validated with experimental data using efficiency and temperature comparison. The developed simulation model is beneficial for designing, optimizing, and developing advanced technology-based inverters to achieve higher efficiency at a particular operating range of temperature and power quality. The new European driving cycle (NEDC) speed profile simulation results are demonstrated.

On the Short Circuit Electro-Thermal Failure of 1.2 kV 4H-SiC MOSFETs with 3D Cell Layouts

In this manuscript, the short circuit (SC) capability of 1.2 kV vertical double diffused SiC MOSFET with different layout topologies is investigated. 3D finite element electro-thermal simulations have been carried out in order to assess the performance of five different cell topologies. It has been found that while the maximum drain current density observed during a SC event agrees well with the specific on-state resistance behaviour, the maximum temperature evolution in the unit cell follows the opposite trend. This behaviour can be explained by the relatively poor spreading of the carriers in the JFET region (of the ALL) at small cell pitches (~ 8um), which can lead to the formation of a filament with a high current density and heat generation.

Electrical and Thermal Characteristics of AlGaN/GaN HEMT Devices with Dual Metal Gate Structure: A Theoretical Investigation

The electrical and thermal characteristics of AlGaN/GaN high-electron mobility transistor (HEMT) devices with a dual-metal gate (DMG) structure are investigated by electrothermal simulation and compared with those of conventional single-metal gate (SMG) structure devices. The simulations reveal that the DMG structure devices have a 10-percent higher transconductance than the SMG structure devices when the self-heating effect is considered. In the meantime, employing the DMG structure, a decrease of more than 11% in the maximum temperature rise of the devices can be achieved at the power density of 6 W/mm. Furthermore, the peak in heat generation distribution at the gate edge of the devices is reduced using this structure. These results could be attributed to the change in the electric field distribution at the gate region and the suppression of the self-heating effect. Therefore, the electrical and thermal performances of AlGaN/GaN HEMT devices are improved by adopting the DMG structure.

A Strategic Pathway from Cell to Pack-Level Battery Lifetime Model Development

The automotive energy storage market is currently dominated by the existing Li-ion technologies that are likely to continue in the future. Thus, the on-road electric (and hybrid) vehicles running on the Li-ion battery systems require critical diagnosis considering crucial battery aging. This work aims to provide a guideline for pack-level lifetime model development that could facilitate battery maintenance, ensuring a safe and reliable operational lifespan. The first of the twofold approach is a cell-level empirical lifetime model that is developed from a lab-level aging dataset of commercial LTO cells. The model is validated with an exhaustive sub-urban realistic driving cycle yielding a root-mean-square error of 0.45. The model is then extended to a 144S1P modular architecture for pack-level simulation. The second step provides the pack electro-thermal simulation results that are upscaled from a cell-level and validated 1D electrical model coupled with a 3D thermal model. The combined simulation framework is online applicable and considers the relevant aspects into account in predicting the battery system’s lifetime that results in over 350,000 km of suburban driving. This robust tool is a collaborative research outcome from two Horizon2020 EU projects—GHOST and Vision xEV, showcasing outstanding cell-level battery modeling accuracies.

A multi-criteria decision analysis of implanted biomedical device antenna: electro-thermal simulation, design, and data analysis

In this article, three elemental (dipole, loop, and meander) designs of an implanted biomedical device (IBD) antenna are studied to provide an enhanced understanding of fundamental (material and geometry) factors which would contribute to the regulation of a steady vital sign, with minimal effect on the surrounding tissue during monitoring and treatment. Dipole and Loop antennas are known to offer similar advantages in that they are both balanced antennas, while the Meander antenna is likely to offer better radiation resistance. The investigation was carried out through the design of experiments and finite element modeling of the temperature field due to the AC level applied (10 or 100mA), under the geometry of each given antenna type and three material options (Titanium, Cobalt Chromium, and Macor). Finally, a multi-criteria decision-making process is applied to select the optimal design under maximum field temperature, thermal conductivity, electrical conductivity, density, and specific heat attributes. The findings suggested that the Meander design made of Titanium would allow for a maximized overall performance with minimal thermal and radiation effects.

Fast Unveiling of T max in GaN HEMT Devices via the Electrical Measurement-Assisted Two-Heat Source Model

Gallium nitride (GaN) high-electron-mobility transistor (HEMT) devices, which have wide application potential from power amplifiers to satellite, need to be thoroughly examined in terms of reliability in order to benefit the superior intrinsic properties of the device. The most critical parameter in the device reliability is the hotspot, or <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {max}}$ </tex-math></inline-formula> , which occurs somewhere on the subsurface and along the channel of the GaN HEMT, which is optically inaccessible due to optical path disability. Therefore, the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {max}}$ </tex-math></inline-formula> value is underestimated in optical measurements, such as the thermographic IR and Raman methods. With 3-D electrothermal simulations, <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {max}}$ </tex-math></inline-formula> is obtained close to reality, but it requires a huge computation load and the complex modeling of semiconductor device physics. In 2-D or 3-D thermal simulations that do not use electrothermal simulations, since the self-heating is mostly modeled with a single heat source, neither the correct <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {max}}$ </tex-math></inline-formula> value is obtained nor the effect of bias conditions is considered. To address the aforementioned shortcomings, a hybrid method is demonstrated, which exploits the electrical measurements of GaN HEMT, which RF and reliability engineers often and easily do. It is demonstrated that <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${T}_{\text {max}}$ </tex-math></inline-formula> can be determined quickly and close to the electrothermal simulations in a GaN HEMT device with a two-heat source method and finite element analysis (FEA) hybrid interaction with respect to various bias conditions. Moreover, the impact of the knee voltage is investigated with different knee-detection techniques. The proposed method provides GaN HEMT reliability engineers with an easy-to-implement alternative to reveal the hotspot location and the value.

Tuning Avalanche Path in Vertical GaN JFETs By Gate Driver Design

The 1.2-kV vertical gallium nitride (GaN) fin-channel junction-gate field-effect transistor (JFET) has recently emerged as a promising candidate for power electronics. It is normally <small>off</small> and has a specific <small>on</small>-resistance smaller than that of 1.2-kV SiC <small>mosfets</small>. A robust avalanche capability has also been reported in vertical GaN JFETs with an avalanche current flowing through the gate. This avalanche path differs from that of power <small>mosfets</small> (via the source) and may pose challenges in gate driver reliability. This article, for the first time, demonstrates that the avalanche current in GaN JFETs can be tuned to flow through the source, by using either a <small>mosfet</small> driver with a large gate resistance or an <i>RC</i>-interface driver. These drivers turn <small>on</small> the fin channel during the device avalanche and obviate a large avalanche current into the gate driver. The carrier dynamics within the GaN JFET under the two avalanche paths have been unveiled by physics-based mixed-mode electrothermal simulations. The critical avalanche energy density in both paths was found to be comparable with the state-of-the-art SiC <small>mosfet</small>s. Additionally, the <i>RC</i>-interface driver was shown to outperform the <small>mosfet</small> driver for vertical GaN JFETs. The learning about normally <small>off</small> GaN JFETs was applied to a study of commercial normally <small>on</small> SiC JFETs. Two avalanche paths of a similar nature were observed with different gate drivers. This article provides new insights of the JFET avalanche and show the excellent robustness of the novel 1.2 kV vertical GaN JFET.

Electro-thermal heating element with a nickel-plated carbon fabric for the leading edge of a wing-shaped composite application

We propose a wing-shaped composite structure that uses an electroless nickel-plated carbon fabric as an electro-thermal heating element, thus improving the electrical and thermal properties. The results showed that the electro-thermal conversion efficiency increased from 0.064 to 0.054 W/°C with increasing plating thickness and weight percentage of the nickel particles deposited. The experiments demonstrated that the surface temperature of the wing-shaped composite could be heated up to 87.9 °C within 1000 s at an applied power density of 2.11 kW/m2. The measurement results agreed well with those of the coupled electro-thermal simulations of heating elements related to a resistance heating phenomenon via an electro-thermal conversion, and it validated the heating performance. In addition, the nickel-plated carbon fabric as a heating element for the leading edge of the wing-shaped model was examined using a multiphysics de-icing simulation under actual icing conditions from a practical perspective. Most of the icing was removed by applying a power density of 2.7 kW/m2 for 600 s to the wing-shaped composite structure. An interlaminar shear strength (ILSS) test was performed to verify the mechanical performance in terms of structural integrity. This practical approach could efficiently offer a desirable solution for the multifunctional de-icing composite field.

Study on operation voltage monitoring and electrothermal coupling simulation of electric multiple unit (EMU) roof arrester

The roof arrester of electric multiple units (EMU) can efficiently limit the overvoltage, and ensure the safe operation of the EMU electrical equipment. In the process of high-speed operation, the traction power supply system is often affected by overvoltage. In addition, roof arrester explosion accidents occasionally occur. In this paper, the on-line voltage measurement system of the EMU arrester is developed. By analysing a large number of voltage waveforms, the abnormal voltage is divided into three categories: over-phase voltage, high harmonic voltage and steep impulse overvoltage. The characteristics of abnormal voltage waveforms are then summarised. The electrothermal coupling simulation model of the arrester is developed, and the current response and temperature distribution of the arrester under abnormal voltage are calculated. The impact of the impulse voltage energy on the arrester temperature is studied by applying a triangular wave voltage to the model. Finally, some suggestions are proposed for the operation and maintenance of the roof arrester.

Simulation-based study of single-event burnout in 4H-SiC high-voltage vertical superjunction DMOSFET: Physical failure mechanism and robustness vs performance tradeoffs

We explore and elucidate physical failure mechanisms in a 4H-SiC, high voltage, superjunction (SJ) vertical DMOSFET from a single heavy ion strike using three-dimensional electro-thermal transient simulations. The single-event burnout (SEB) failure is thermal runaway from second breakdown, initiated by impact ionization and terminated with mesoplasma formation, at the center of the P-pillar/N+ substrate interface. We also demonstrate that the SEB performance of this SiC SJ DMOSFET is insensitive to the pillar width but sensitive to the strike location with ion strike at the P-pillar causing SEB at a lower blocking voltage than at the N-pillar. Compared to commercially available 1.2 kV blocking-rated non-SJ DMOSFETs, which have been demonstrated to survive SEB up to 525 V, the SJ DMOSFET increases SEB survival threshold voltage (VSEB) by a factor of 2.2, making it close to 1200 V, while the on-resistance is increased by only 11%. Using our recently developed figure of merit (FoM), which considers the trade-off between VSEB and on-state performance, we find that the SiC SJ DMOSFET achieves a FoM that is 14 times better, making it superior to conventional 1.2 kV SiC DMOSFETs for long-term radiation-tolerant operation in space applications.

Electric field simulations of field grading techniques in HVDC cable joints

PurposeIn high voltage direct current cable systems, cable joints are known as the least reliable components due to the use of multiple dielectrics. Resulting from the electric field and temperature depending conductivity of the different dielectrics, field enhancement at critical areas, e.g. triple points, may result in accelerated aging and the failure of the component. To reduce the stress, different field grading techniques are applied. The purpose of this study is to investigate different grading techniques for cable joints. Different shapes of the electrode and a varying nonlinear conductivity of field grading materials (FGM) are used for the simulation of the electric field.Design/methodology/approachCoupled electro-thermal field simulations are applied for different joint geometries, to obtain the stationary electric field. Electric field simulations in cable joint using geometric and nonlinear field grading techniques are shown.FindingsUsing the geometric field grading, the shape of the stress cone determines the field values in critical areas (triple points). High stress reduction is obtained for a certain curvature of the stress cone. For the nonlinear stress control, materials with a higher conductivity in comparison to the cable and the joint material are used. A field reduction is obtained by increasing the total conductivity. On the other hand, this is also increasing the insulation losses within the total FGM. More applicable is the decrease of the switching field or the increase of nonlinearity, which is only locally increase the conductivity and the insulation losses. Furthermore, simulations results show that an approximately constant field reduction is obtained, if the nonlinearity is above a certain threshold.Research limitations/implicationsThis study is restricted to a field dependency of FGM only. For impulse voltages, high temperature and electric conductivity values my result in a thermal runaway. Furthermore, only direct current field grading techniques are studied.Originality/valueThe field grading of cable joints, using geometric and nonlinear techniques, is analyzed. A comparison between the electric field, by varying the curvature of the ground stress cone or the FGM conductivity constants in a complex joint geometry is novel. With its effect on the electric fields, general requirements for the geometry (geometric field grading) or the values of the FGM constants (nonlinear field grading) are defined to obtain a sufficient field grading.

Influence of the Metal–Semiconductor Interface Model on Power Conservation Principle in a Simulation of Bipolar Devices

The purpose of the study is to present a proper approach that ensures the energy conservation principle during electrothermal simulations of bipolar devices. The simulations are done using Sentaurus TCAD software from Synopsys. We focus on the drift-diffusion model that is still widely used for power device simulations. We show that without a properly designed contact(metal)–semiconductor interface, the energy conservation is not obeyed when bipolar devices are considered. This should not be accepted for power semiconductor structures, where thermal design issues are the most important. The correct model of the interface is achieved by proper doping and mesh of the contact-semiconductor region or by applying a dedicated model. The discussion is illustrated by simulation results obtained for the GaN p–n structure; additionally, Si and SiC structures are also presented. The results are also supported by a theoretical analysis of interface physics.

Investigation and Modeling of the Avalanche Failure Mechanism of 1.2-kV 4H-SiC JMOS

We studied the avalanche failure mechanism of a 1.2-kV 40-A monolithic junction barrier-controlled Schottky-diode-integrated SiC MOSFET (JMOS) using a single-pulse unclamped inductive switching (UIS) test to evaluate its avalanche ruggedness. The avalanche electro-thermal (AET) model was established to illustrate the transient electro-thermal behavior in single-pulse avalanche stress to present the thermal runaway failure process of the JMOS and obtain the dynamic temperature function during UIS. The AET model also proposes a critical failure temperature of 1240 K for determining the failure region. The electro-thermal TCAD mixed mode simulation study demonstrates that the critical temperature and failure area appear in the Schottky barrier diode (SBD) region, which is also verified by a focused-ion beam (FIB) microsection analysis. The enhancement of avalanche ruggedness of JMOS can be achieved by adjusting the properties of the SBD region.

Analysis of Transient Surge Current Mechanism in SiC MPS Diode With the Transition Region

In this work, Sentaurus TCAD was used to study the transient surge current mechanism of the 4H-SiC merged pin and schottky (MPS) diode. For the first time, a structure combining multicells with transition region was used to analyze the transient surge current mechanism of the MPS diode. The electrothermal simulation analysis of the surge characteristics of the MPS diode is carried out. Internal carrier distribution and lattice temperature in the surge current transient process of the device are mainly studied. The simulation results show that the hole current distribution and the electron current distribution in the MPS diode are not uniform. In the transient process of surge current, the transition region first enters the bipolar conduction mode, and then, the cells in the active region enter the bipolar conduction mode in the order from outside (close to transition region) to inside. The voltage-time (V-t), maximum temperature-time ( $T_{max}$ -t), and I-V curves of MPS diode in surge current events are obtained by simulation. Combined with the current density distribution diagram, the device behavior of multiple critical time nodes is analyzed in detail, and a reasonable explanation is given. In addition, the influence of different transition region contact types on the internal current distribution of the MPS diode is studied, and the simulation results are reasonably explained.

Multiphysics Optimization of Thermal Management Designs for Power Electronics Employing Impingement Cooling and Stereolithographic Printing

Meeting the stringent performance requirements for power electronic converters in electric vehicles requires an integrated approach for optimizing the inherently coupled electrical and thermal performances of converter systems. This article presents a multidisciplinary thermal management design methodology that utilizes genetic algorithms (GAs) to generate topologically optimized geometries for liquid-cooled heat sinks. These GA-generated heat sinks are based on impingement cooling principles and leverage the flexibility of stereolithographic manufacturing techniques. The proposed optimization methodology incorporates the interdependence between the thermal and electrical aspects of the system, and it is capable of targeting performance metrics in either or both domains. This optimization process is demonstrated for a 6.6-kW integrated power module design employing bare-die silicon carbide devices on an FR4-based printed circuit board with embedded ceramic elements. Experimentally validated electrothermal multiphysics simulations of the GA-optimized heat sinks targeting various performance metrics show successful optimization of targeted metrics relative to the initial seed design. The results demonstrate the importance of the multidisciplinary design approach and the effectiveness of the GA-based optimization methodology.

A Hybrid Streamline Upwind Finite Volume-Finite Element Method for Semiconductor Continuity Equations

This article presents the construction and analysis of a hybrid numerical method for the discretization of the convection-dominated nonlinear carrier transport process in semiconductor devices. In the construction of the method, the edge streamline upwind (SU) current density model is employed to overcome the nonconvergence brought by the nonlinear property of the current continuity equation, and the mixed finite volume-finite element method (FVFEM) is utilized to effectively extend the edge SU current density model to multidimensional applications. The proposed method is more reliable and flexible than the finite box (FB) method and streamline upwind Petrov–Galerkin (SUPG) method. The performance of several popular SU current density models is compared to find the optimal one. The proposed method is validated by comparing the calculated results with those calculated using commercial software. Based on the streamline upwind-finite volume-finite element method (SU-FVFEM), the finite element method (FEM), and the domain decomposition method (DDM), an in-house parallel computing electrothermal simulator is developed for large-scale semiconductor devices. The performance of the in-house developed parallel simulator is evaluated through simulations of a p-n junction diode and a 3-D bipolar transistor. The results demonstrated that the developed parallel simulator possesses good accuracy, applicability, and scalability.

A Novel MOS-Channel Diode Embedded in a SiC Superjunction MOSFET for Enhanced Switching Performance and Superior Short Circuit Ruggedness

In this study, a novel MOS-channel diode embedded in a SiC superjunction MOSFET (MCD SJ-MOSFET) is proposed and analyzed by means of numerical TCAD simulations. Owing to the electric field shielding effect of the P+ body and the P-pillar, the channel diode oxide thickness (tco) of MCD can be set to very thin while achieving a low maximum oxide electric field (EMOX) under 3 MV/cm. Therefore, the turn-on voltage (VF) of the proposed structure was 1.43 V, deactivating the parasitic PIN body diode. Compared with the SJ-MOSFET, the reverse recovery time (trr) and the reverse recovery charge (Qrr) were improved by 43% and 59%, respectively. Although there is a slight increase in specific on-resistance (RON), the MCD SJ-MOSFET shows very low input capacitance (CISS) and gate to drain capacitance (CGD) due to the reduced active gate. Therefore, significantly improved figures of merit RON × CGD by a factor of 4.3 are achieved compared to SJ-MOSFET. As a result, the proposed structure reduced the switching time as well as the switching energy loss (ESW). Moreover, electro-thermal simulation results show that the MCD SJ-MOSFET has a short circuit withstand time (tSC) more than twice that of the SJ-MOSFET at various DC bus voltages (400 and 600 V).

Investigating the Impact of Self-Heating Effects on some Thermal and Electrical Characteristics of Dielectric Pocket Gate-all-around (DPGAA) MOSFETs

The dielectric pocket gate-all-around (DPGAA) MOSFET is being considered the best suited candidate for ULSI electronic chips because of excellent electrostatic control over the channel. However, the phenomena of self-heating and hot carrier injection (HCI) severely affect the performance of the device, and make the behaviour of the DPGAA FET very unpredictable. In the present article, a comprehensive investigation under the influence of self-heating effects has been done for the variation in the lattice and carrier temperature against spacer length, ambient temperature, device length, and thermal contact resistance including ON and Off currents with gate bias voltage (VGS). In order to analyse the SHEs, the hydrodynamic (HD) and thermodynamic (TD) transport models have been used for three-dimensional (3D) electrothermal (ET) simulation. The Lucky (hot carrier injection) model has been used to study the HCI degradation in DPGAA MOSFET using Sentaurus 3D TCAD simulator.