Investigation and Modeling of the Avalanche Failure Mechanism of 1.2-kV 4H-SiC JMOS

Abstract

We studied the avalanche failure mechanism of a 1.2-kV 40-A monolithic junction barrier-controlled Schottky-diode-integrated SiC MOSFET (JMOS) using a single-pulse unclamped inductive switching (UIS) test to evaluate its avalanche ruggedness. The avalanche electro-thermal (AET) model was established to illustrate the transient electro-thermal behavior in single-pulse avalanche stress to present the thermal runaway failure process of the JMOS and obtain the dynamic temperature function during UIS. The AET model also proposes a critical failure temperature of 1240 K for determining the failure region. The electro-thermal TCAD mixed mode simulation study demonstrates that the critical temperature and failure area appear in the Schottky barrier diode (SBD) region, which is also verified by a focused-ion beam (FIB) microsection analysis. The enhancement of avalanche ruggedness of JMOS can be achieved by adjusting the properties of the SBD region.