Failure Mechanism Analysis of SiC MOSFETs in Unclamped Inductive Switching Conditions

Abstract

In this work, avalanche ruggedness and failure mechanism of SiC MOSFET in single-pulse Unclamped Inductive Switching (UIS) tests are investigated and compared with that of Si IGBT. The experimental results show that the avalanche energy of SiC MOSFET is only 30% that of Si IGBT due to the much smaller chip size (1/7 that of Si IGBT). To improve the avalanche capability of SiC MOSFET, the failure mechanism is analyzed. First, junction temperature in the UIS test is calculated through modeling. The maximum junction temperatures reach 650 K and 490 K in SiC MOSFET and Si IGBT, respectively. Then, BJT latch-up probability is analyzed with an analytical model. It is demonstrated that BJT latch-up can be triggered at the failure temperature (650 K) in SiC MOSFET, whereas it can be eliminated in Si IGBT due to the much deeper P+ body structure. Based on the analyses, the device structure optimization is proposed for SiC MOSFET to prevent the BJT latch-up and enable avalanche capability improvement.