Electrostatic Discharge Test Research Articles

New Low-Leakage Power-Rail ESD Clamp Circuit in a 65-nm Low-Voltage CMOS Process

A new low-leakage power-rail electrostatic discharge (ESD) clamp circuit designed with consideration of the gate leakage issue has been proposed and verified in a 65-nm low-voltage CMOS process. Consisting of the new low-leakage ESD-detection circuit and the ESD clamp device of a substrate-triggered silicon-controlled rectifier, the new proposed power-rail ESD clamp circuit realized with only thin-oxide (1-V) devices has a very low leakage current of only 116 nA at room temperature (25°C ) under the power-supply voltage of 1 V. Moreover, the new proposed power-rail ESD clamp circuit can achieve ESD robustness of over 8 kV, 800 V, and over 2 kV in human-body-model, machine-model, and charged-device-model ESD tests, respectively.

Systematic Analysis Methodology for Mobile Phone's Electrostatic Discharge Soft Failures

A systematic analysis methodology for mobile phone's electrostatic discharge (ESD) soft failures is proposed. The proposed analysis methodology consists of two parallel processes: one is the ESD simulation and the other is the ESD characterization of the mobile phone. The ESD simulation models that consist of the ESD generator, the ESD testing setup, and a mobile phone are also developed and their accuracy is experimentally verified. The proposed methodology is applied to design the countermeasures against the ESD soft failure of the slide-type mobile phones and the root causes of the ESD soft failures are analyzed. The RC low-pass filters are designed to improve the ESD immunity of the mobile phone and the ESD simulation results of the improved mobile phone show more than 82% voltage-level reductions of the signals, which cause the ESD soft failures. In order to verify that the reduced voltage levels, actually, solve the problem of ESD soft failures, the improved mobile phone's ESD immunity is characterized again, and no ESD soft failure is detected.

Effects of Concentration of Nanoscale Tin-Doped Indium Oxide on Electrical Breakdown of High-Resistance Liquid Crystal

According to our previous study, a high concentration of nanoscale tin-doped indium oxide (ITO) may be beneficial for protecting liquid crystal (LC) against attacks by electrostatic discharge (ESD). In this study, the influence of high-voltage stresses in an ESD test was investigated for cells doped with different concentrations of ITO. It was found that nano-ITO with a concentration of 0.4% in weight ratio deteriorated the physical properties of LC of transparency transition and charge retention. However, our experiment showed that the capability of ESD protection for the doped LC was still improved at the ITO concentration of 0.4 wt %. This finding supports the proposed model in our previous report. The role of ITO in the LC is not always beneficial, as discussed in this paper.

Low-Capacitance Low-Voltage Triggered SCR ESD Clamp Using nMOS With Asymmetric Drain for RF ICs

A novel low-capacitance low-voltage triggered silicon-controlled rectifier (LC-LVTSCR) electrostatic discharge (ESD) clamp is proposed in a 0.13-μm RF process. The proposed ESD clamp meets the ESD robustness and the RF requirement. The mechanism of the proposed LC-LVTSCR is investigated by T-CAD simulations, and a method to reduce the parasitic capacitance is presented. From the measurement, it was observed that the proposed ESD clamp has approximately 50% lower parasitic capacitance compared to the conventional LVTSCR device. The proposed ESD clamp was successfully used in a 2.4-GHz RF transceiver chip. The RF chip with the new proposed LC-LVTSCR passed a human body model 1-kV and machine model 100-V ESD test.

1 fF ESD protection device for gigahertz high-frequency output ESD protection

A mutual-protection scheme is proposed to achieve an ultra-low capacitance electrostatic discharge (ESD) protection device. The ESD protection device can not only dissipate ESD current, but also can make the vulnerable output transistor have the ESD protection capability. Namely, the output transistor can also protect ICs and help the ESD protection device to share the ESD current. Using this scheme can discharge more ESD current than the summation current of the two individual devices. From the ESD test result, it can achieve the required ESD level by using the ultra-low capacitance ESD protection device (∼1.2 fF).

ESD Protection Design With Lateral DMOS Transistor in 40-V BCD Technology

An electrostatic discharge (ESD) protection design for smart power applications with lateral double-diffused MOS (LDMOS) transistors is investigated. With the gate-driven and substrate-triggered circuit techniques, the n-channel LDMOS can be quickly turned on to protect the output drivers during an ESD stress event. The proposed gate-driven and substrate-triggered ESD protection circuits have been successfully verified in a 0.35-μm 5 V/40 V bipolar CMOS DMOS (BCD) process, which can sustain ESD voltages of 4 kV in human-body-model (HBM) and 275 V in machine-model (MM) ESD tests. In addition, the power-rail ESD protection design can also be achieved with a stacked structure to protect 40-V power pins without a latchup issue in the smart power integrated circuits.

The Effect of Approach Speed and Charge Voltage on an Air Discharge

In this paper, a new electrostatic discharge (ESD) testing system is designed and the influence of the approach speed and charge voltage on ESD parameters, e.g., discharge current, rise time, and induced voltage in a semicircular loop antenna, and also the reproducibility of experimental results are analyzed. It is concluded that, as the charge voltage is constant, ESD parameters are linearly proportional to the approach speed, the reproducibility increases with growth of the approach speed, especially at 0.8 m/s. As the approach speed is constant, the field strength generated at low charge voltage is stronger than that at high charge voltage; better reproducibility can be also reached at low charge voltage. These important conclusions provide the foundation for developing standard method for air ESD immunity tests.

Application of Machine Model ESD tester to high volume capacitor reliability testing

Electro-Static Discharge (ESD) is a common cause of failure for RF semiconductors during module assembly processes and service of the RF modules in end-customer applications (i.e. field service). To develop and verify semiconductor capacitor designs with sufficient ruggedness to withstand a given ESD environment during customer assembly and field service, sufficient quantities of devices need to be tested to determine larger failure voltage distributions rather than the minimal three required for product qualification (Electrostatic Discharge (ESD) [1,2]). Using ESD voltage breakdown testing one can more precisely and statistically simulate actual field failures when compared to testing on-wafer DC ramp-to-failure voltage (Whitman et al., 2004 [3]).

New Transient Detection Circuit for On-Chip Protection Design Against System-Level Electrical-Transient Disturbance

A new transient detection circuit for on-chip protection design against system-level electrical-transient disturbance is proposed in this paper. The circuit function to detect positive or negative electrical transients under system-level electrostatic-discharge (ESD) and electrical-fast-transient (EFT) testing conditions has been investigated by HSPICE simulation and verified in silicon chip. The experimental results in a 0.18-μm complementary-metal-oxide-semiconductor (CMOS) process have confirmed that the new proposed on-chip transient detection circuit can successfully memorize the occurrence of system-level electrical-transient disturbance events. The output of the proposed on-chip transient detection circuit can be used as a firmware index to execute the system recovery procedure. With hardware/firmware codesign, the transient disturbance immunity of microelectronic products equipped with CMOS integrated circuits under system-level ESD or EFT tests can be significantly improved.

Impact of design factors and environment on the ESD sensitivity of MEMS micromirrors

In this paper, electrostatic discharge (ESD) tests on electrostatically actuated torsional micromirrors are performed in various pressure conditions and the ESD failure levels are reported for the first time in literature. The influence of device design factors of the micromirror, such as the torsional hinge width and the actuation bottom electrode area, on the ESD sensitivity is investigated. HBM ESD stress tests are performed in standard atmospheric pressure and in vacuum. These design parameters and the ambient pressure conditions are shown to affect the ESD failure levels of the MEMS micromirrors. Two distinct failure signatures are observed for micromirrors, viz., pull-in and sticking to the bottom electrode or getting destroyed and broken under the impact of the ESD stress.

Alternative method for electrostatic discharge stress testing of individual system components

Electrostatic discharge (ESD) testing of integrated circuits (ICs) is necessary to ensure that the products can withstand several types of ESD threats, including those encountered in the factory and in the field. This study discusses the testing of components with electrostatic stress waveforms that were originally designed for predicting system failures in the field. IC manufacturers are struggling to obtain reliable data when applying system tests to their components due to interface and repeatability problems found with this form of evaluation. To alleviate these problems and some of the confusion, a new test methodology has been designed and implemented. It is used for testing individual components that have pins that are to be connected to the external ports on a completed design. This study reports on a new method that solves these IC testing problems and compares it to the current approach most often employed.

A Practical, Innovative Method for Electro-Static Discharge Data Analysis

A practical method to identify outliers in interval data mixed with some right censored data is proposed. It is based on a simple concept of determining the probability that a deviation of an outlier, by chance, from the probability line which was fitted by the data set with the outlier deleted. The median rank method is employed to determine its sample failing fraction to construct the probability plot. A special treatment is employed to treat the suspect outlier when making probability plots and regression with the suspect outlier deleted. The Fisher Matrix is used to determine the confidence bound, and to assist the estimation of the probability. A critical interval is then defined based on the calculated confidence bound in ESD (Electrostatic Discharge) data, and then the complicated methods are simplified with a simple linear regression using Excel to determine the distance that the possible outlier deviates from the regression line. The remaining work is to simply compare the distance with the critical interval before making a decision about what to do next, such as re-do ESD tests or refine ESD circuits, perform troubleshooting on the manufacturing process, and/or implement process changes for the IC product's ESD performance improvement.

Soft and Hard Failures of InGaN-Based LEDs Submitted to Electrostatic Discharge Testing

This letter reports an extensive analysis of the degradation mechanisms of InGaN-based light-emitting diodes (LEDs) submitted to reverse-bias electrostatic discharge (ESD). The results of this analysis indicate that two different failure modes, namely, “soft” and “hard” degradations, can be induced by ESD pulses. The “soft” failure mode takes place as a consequence of ESD events with moderate voltage/current levels and consists in a decrease in the reverse-bias leakage current of LEDs. This effect is due to the annihilation of some of the defective paths responsible for leakage-current conduction, possibly triggered by the injection of relatively high reverse-bias current densities. “Hard” failure takes place when high-voltage/current ESD pulses are applied to an LED. After hard failure, LEDs behave as short circuits. This process is due to the high voltage levels reached by the junction during an ESD event (with subsequent dielectric rupture) or to the injection of extremely high current densities through one of the localized paths responsible for reverse-current conduction.

Dependence of facet stress on reliability of AlGaInAs edge-emitting lasers

The relationship between facet stress and reliability of AlGaInAs edge-emitting lasers is unclear despite it being an important issue. We prepared two 1.3 μm AlGaInAs Fabry–Pérot buried-heterostructure (BH) lasers that were identical except that they had tensile and compressive stress at the facet. The magnitude of the facet stress was controlled to be approximately 200 MPa in both lasers. We performed three reliability tests. In forward-biased electrostatic discharge tests, which can evaluate the resistance to optical damage, the cumulative degradation ratio of the compressive stressed laser was 33% lower than that of the tensile stressed laser. This result indicates a reduction in the optical absorption due to enlargement of the energy band gap at the facet. In the long-term aging of the light output power of 8 mW at 85 °C over 5 000 h, no dependence of the facet stress on the lifetime was observed. Since a major limitation of InP-based BH lasers is the BH interface, the aging results are reasonable. In the accelerated aging of a large current of 200 mA at 85 °C over 800 h, degradation (defined as an increase in the threshold current of over 10%) was observed only in the tensile stressed laser. This degradation differed completely from that caused by optical absorption; dislocation loops covered the entire active layer at the facet. To the best of our knowledge, this is the first time such degradation has been reported. We found the degradation depends on the facet stress and that compressive stress can suppress the degradation.

A Case Study of Problems in JEDEC HBM ESD Test Standard

There is a current need for modification of EIA/JEDEC Human-Body model (HBM) electrostatic discharge (ESD) test standard, which does not define start and step test voltages. In the current standard, some measurements start at several kilovolts, which ignore the fact that ESD protection devices may fail under low voltage stresses. In this paper, a grounded-gate structure with an n-well ballast resistor connecting its drain and PAD is investigated for HBM ESD sustaining levels. When tested with a Zapmaster starting from 1 kV, the withstand voltage exceeds 8 kV, whereas the structure failed at 350 V when the test starts from 50 V. The test results from a transmission-line-pulsing system validate the phenomenon. The reason for the failure is also studied and confirmed with optical-beam-induced resistor change system failure analysis results. To address this general issue, a suggestion for improving the present HBM ESD testing standards for industry applications is made.

Do ESD fails in systems correlate with IC ESD robustness?

Integrated circuits (ICs) are qualified for their electrostatic discharge (ESD) robustness according to the well-known IC ESD standards Human Body Model, Machine Model, and Charged Device Model in order to guarantee safe handling in ESD protected areas. For electronic systems like mobile phones which are in direct use by consumers, certain robustness against system level ESD is demanded, too. As the ESD test methods of device and system level stress are completely different (waveforms, stress application, operating condition of the DUT, etc.), correlations between models of both worlds are difficult to establish. Therefore, the system vendors more and more demand a specified ESD robustness for devices (ICs) according to an ESD system level standard. Testing ICs to a system level ESD standard requires careful considerations; first ideas are summarized in the new Standard Practice “Human Metal Model” of the ESDA/ANSI. However, the approach of deriving system ESD robustness from IC robustness is currently too much simplified and bears severe potential risks. Nevertheless, there are methodologies and approaches to use IC ESD characterization for defining ESD protection concepts for systems. Appropriate high-current characterization of ICs can be the cornerstone for a successfully optimized system ESD protection.

Transient-to-Digital Converter for System-Level Electrostatic Discharge Protection in CMOS ICs

A new on-chip RC-based transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed, which can detect fast electrical transients during the system-level ESD test. A novel on-chip transient-to-digital converter composed of four RC-based transient detection circuits and four different RC filter networks has been successfully designed and verified in a 0.18- mum CMOS process with 3.3-V devices. The output digital thermometer codes of the proposed on-chip transient-to-digital converter correspond to different ESD voltages under system-level ESD tests. The proposed on-chip transient-to-digital converter can be further combined with firmware cooperation to provide an effective solution to solve the system-level ESD protection issue in microelectronic systems equipped with CMOS ICs.

Accelerated lifetime test of RF-MEMS switches under ESD stress

This paper presents the results of a study on issues of reliability and accelerated life testing for radio frequency micro-electromechanical system (RF-MEMS) capacitive devices. A human-body-model electrostatic discharge tester has been used to induce charging by operating at stress levels much higher than would be expected in normal use. Temperature ranges from 300 K to 330 K allows the understanding of physical mechanisms that may be responsible for the device’s reliability.

A 5-GHz Differential Low-Noise Amplifier With High Pin-to-Pin ESD Robustness in a 130-nm CMOS Process

Two electrostatic discharge (ESD)-protected 5-GHz differential low-noise amplifiers (LNAs) are presented with consideration of pin-to-pin ESD protection. The pin-to-pin ESD issue for differential LNAs is addressed for the first time in the literature. Fabricated in a 130-nm CMOS process, both ESD-protected LNAs consume 10.3 mW under 1.2-V power supply. The first LNA with double-diode ESD protection scheme exhibits the power gain of 17.9 dB and noise figure of 2.43 dB at 5 GHz. Its human-body-model (HBM) and machine-model (MM) ESD levels are 2.5 kV and 200 V, respectively. With the same total parasitic capacitance from ESD protection devices, the second LNA with the proposed double silicon-controlled rectifier (SCR) ESD protection scheme has 6.5-kV HBM and 500-V MM ESD robustness, 17.9-dB power gain, and 2.54-dB noise figure at 5 GHz. The ESD test results have shown that the pin-to-pin ESD test is the most critical ESD-test pin combination for the conventional double-diode ESD protection scheme. With the proposed double-SCR ESD protection scheme, the pin-to-pin ESD robustness can be significantly improved without degrading RF performance. Experimental results have shown that the ESD protection circuit for LNA can be co-designed with the input matching network to simultaneously achieve excellent ESD robustness and RF performance.

Environmental Effects on Solar Array Electrostatic Discharge Current Waveforms and Test Results

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