Low-Capacitance Low-Voltage Triggered SCR ESD Clamp Using nMOS With Asymmetric Drain for RF ICs

Abstract

A novel low-capacitance low-voltage triggered silicon-controlled rectifier (LC-LVTSCR) electrostatic discharge (ESD) clamp is proposed in a 0.13-μm RF process. The proposed ESD clamp meets the ESD robustness and the RF requirement. The mechanism of the proposed LC-LVTSCR is investigated by T-CAD simulations, and a method to reduce the parasitic capacitance is presented. From the measurement, it was observed that the proposed ESD clamp has approximately 50% lower parasitic capacitance compared to the conventional LVTSCR device. The proposed ESD clamp was successfully used in a 2.4-GHz RF transceiver chip. The RF chip with the new proposed LC-LVTSCR passed a human body model 1-kV and machine model 100-V ESD test.