Electrostatic Discharge Test Research Articles

Research on the electro-magnetic protection technique of SCB bridge based on vertical punch through PN junction

Pyrotechnic device is the key initiating component of weapon system, and its function reliability will directly affect the triggering of detonation and actuation mechanism. In order to enhance the survival ability of pyrotechnic device in intricate electromagnetic interference environment, it is necessary to carry out in-depth research on the electromagnetic protection technique of pyrotechnic device. In this paper, a new electromagnetic protection circuit based on vertical punch through PN junction device is proposed, which monolithically integrates the circuit with polysilicon semiconductor bridge on a single chip. The Electro-static Discharge (ESD) test was carried out according to the method specified by standard electrostatic standard 500 pF/500 Ω/25 kV, and the ESD capability of the proposed new chip was not less than 25 kV. Compared with the electromagnetic protection circuit by transient voltage suppressor diode based on lateral punch through junction device structure, the new chip increases the effective junction area of PN junction, reduces the current density, and increases the current conduction ability and electrostatic roughness of the diode. The new chip has a larger diode effective junction capacitance, which not only improves the ESD capability but also improves the RF protection capability at the same time.

A modular and scalable system for electromagnetic compatibility testing of integrated circuits

To bring automotive integrated circuits (ICs) to market, manufacturers must subject their products to numerous electromagnetic compatibility (EMC) tests such as electromagnetic immunity and emission tests, or electrostatic discharge (ESD) tests. These tests need EMC test boards that meet the requirements of the specific standards. However, the current need to increase the frequency range of EMC tests poses a challenge in designing standard-compliant test boards. In this paper, we address this issue by introducing a modular and reusable IC level EMC test system. We demonstrate the system’s effectiveness with an example of two frequently used and conducted EMC tests: the direct power injection (DPI) immunity test and the 150Ω\\documentclass[12pt]{minimal} \\usepackage{amsmath} \\usepackage{wasysym} \\usepackage{amsfonts} \\usepackage{amssymb} \\usepackage{amsbsy} \\usepackage{mathrsfs} \\usepackage{upgreek} \\setlength{\\oddsidemargin}{-69pt} \\begin{document}$$150\\,\\mathrm{\\Omega}$$\\end{document} electromagnetic emission measurement. The two test setups are constructed and validated using the presented modules. It is shown how the frequency range can be expanded while minimizing costs and design efforts for the EMC test board design.

Establishment of analytical model for electrostatic discharge gate-to-source capacitance of power metal-oxide-semiconductor field-effect transistor

In the actual human body model (HBM) test, it is found that the electrostatic discharge (ESD) test results of various power metal-oxide-semiconductor field-effect transistor (MOSFET) devices show asymmetry between forward withstand voltage and reverse withstand voltage, while the ESD process does not distinguish between positive direction and negative direction. Large differences between forward and reverse withstand voltages are unacceptable for power MOSFETs or as ESD protection devices. The problem of its causing device failure is particularly pronounced. In this work, by establishing the analytical model of gate-to-source capacitance of SGT-MOSFET, VUMOSFET and VDMOS under the forward and reverse voltages, we comparatively analyze the reasons for the asymmetry of the forward and reverse withstand voltages and their different ratios of the three kinds of power MOSFETs, which provides a theoretical basis for testing the device’s ESD and the analyzing their reliability. It is found that the ESD forward and reverse withstand voltage asymmetry phenomena of different power MOSFET structures are related to the variation of gate-to-source capacitance, caused by the reverse-type layer. When a forward voltage is applied across the gate and source, the device gate-to-source capacitance consists of the oxide layer capacitance around the gate in parallel; when a reverse voltage is applied, the gate-to-source capacitance consists of the virtual gate-to-drain capacitance in series with the inverse layer capacitance and then in parallel with the other oxide layer capacitance around the gate. This results in a decrease of the gate-to-source capacitance at the reverse voltage, making the device reverse withstand voltage greater than the forward withstand voltage. The difference in the ratio of ESD reverse withstand voltage to forward withstand voltage among different devices is related to the change of the capacitance of the inverse layer in the gate-to-source capacitor under reverse voltage caused by the difference in device structure.

ESD Research of SCR Devices under Harsh Environments.

In prior technology, system-level electrostatic discharge (ESD) tests under environment change conditions mainly focused on testing the effect of a high-temperature environment. i.e., the effect on internal circuits of heat generated outside. However, few studies have explored the effect of ambient relative humidity changes on integrated circuits (ICs). Therefore, this study will analyze the performance of various ESD protection components under high ambient temperature and high ambient relative humidity. The ESD protection devices are tested for the ESD robustness of the silicon-controlled rectifiers (SCR) under a harsh environment and the measurement results are discussed and verified in the CMOS process.

Fabrication and performance of a nickel-chromium (NiCr) igniter integrated with TVS diode for ESD protection

The NiCr igniter is a key element of MEMS-based electro-explosive device (mEED), while electrostatic discharge (ESD) may excite the igniter accidentally. To protect the NiCr igniter from damage by ESD, a novel NiCr igniter by integrating the igniter onto a TVS diode based substrate was designed and fabricated through semiconductor technology. The microscope photograph, resistivity, breakdown voltage, firing performance, and ESD protection ability were tested. The results show that the surface of the chip is smooth, the edges of key structures are clear, and there are no major scratches, cracks, and other phenomena on the whole device. The resistivity of all the TVS-mNiCr igniters is between 5 and 7 Ω, and the TVS diode resistance value is normal. The breakdown voltages of the eight types of TVS diodes with different structures are all between 3.5 and 5 V, and the TVS-mNiCr igniters can fire reliably at a constant current of 2 A. After the ESD test, the microscope of the igniter does not change significantly, meaning that the TVS-mNiCr igniter chip has a certain ability of ESD protection. It is of vital importance to guide the design of electrostatic tolerant ability for the MEMS-based electro-explosive device.

Electrostatic Discharge Tests of Carbon Composite Materials with Conductive Resin

Carbon fiber composite is an increasingly common spacecraft material due to its favorable mechanical, thermal, and Radio Frequency (RF) properties. Despite the intrinsically conductive nature of the carbon fibers, it has been shown that the dielectric resin that binds the laminate together can cover much of the surface of the finished structure and pose a serious electrostatic discharge (ESD) concern. Previously recommended ESD mitigations such as abrading off the surface resin or applying a static-dissipative coating to the surface of the structure may not be amenable to all spacecraft design needs, and can be difficult to implement. The ideal solution to the carbon composite ESD problem is a material made entirely of constituents conductive enough not to pose any risk of ESD. We present test results for two carbon composite materials with conductive resins, PMT-F6-CL100 and PMT-F6-BP1, that do not discharge under severe electron exposure at cryogenic temperatures, conditions under which a standard formulation PMT-F6 produced copious discharges.

Accurate and Efficient Computation of System-Level ESD Noise Waveforms in ISO 10605 Standard Using Decomposition Method and Split-Domain Approach

In this article, an accurate and efficient computational method of system-level electrostatic discharge (ESD) noise waveforms in a field-coupled ESD test of the ISO 10605 standard using a 3-D full-wave solver is proposed. To apply efficient computational methods to the ESD test simulation, the split-domain approach and decomposition method are first individually validated with a simple structure. Next, a method simultaneously using the decomposition method and split-domain approach is proposed and validated with the separately given field source data. Using the proposed method with the measured electromagnetic fields radiated from an ESD generator, the ESD noise waveforms in the ISO 10605 field-coupled ESD test are accurately and efficiently computed by considering not only the ESD current coupling but also the radiated coupling from the ESD generator.

Circuit-Aided Dummy Design for Human Body-Worn ESD Application

Electrostatic discharge (ESD) is considered for different postures of the body and for different positions of a device under test (DUT). These scenarios lead to large variations in peak discharge currents, and a traditional commercial ESD generator cannot test these satisfactorily. Instead of using actual humans, a full-size dummy has been designed for different body-worn ESD test scenarios, its discharge currents and fields are verified by comparing the measurement results with those taken from volunteers. A wearable DUT on the wrist, elbow, and waist is taken into consideration to compare the characteristics of the dummy to those of the real human body. Furthermore, a circuit model is proposed to aid in understanding the dummy design and the different body-worn scenarios. Finally, the effect of an external connection with different waist positions is analyzed and discussed in a more complex application scenario.

Editorial Introduction to the Special Issue on Electrostatic Discharge and Immunity—From IC to System

The papers in this special issue focus on scientific contributions in the field of electrostatic discharge (ESD) and immunity—from integrated circuits (ICs) to system. ESD can damage or disrupt electronic systems. With continued scaling of ICs, a combined approach of IC and system forms the best path for understanding and ensuring robustness. This relates to the IC itself: input/output (I/O) structures, power distribution network (PDN), interfaces between IP blocks, as well as the interaction of external protection devices with internal ESD protection structures during system level stress. To effectively protect the ICs fabricated in the advanced nanoscale CMOS processes, the turn-on speed of ESD protection devices must be enhanced to quickly discharge ESD current before the internal circuits are damaged by ESD stresses. Not only component level ESD events, the system level ESD test specified in the IEC 61000-4-2 standard has been used to verify ESD immunity of the microelectronics products. During system level ESD testing, the ESD problems relates to soft failures. So far, only few models for soft failures have been reported. It becomes visible that well designed hard failure protection can also reduce the likelihood of soft failures as most of the current is diverted from the IC and will not disturb the PDN of the IC. ESD robustness in the system level and component level are both important to meet the electromagnetic compatibility (EMC) regulations and/or standards in the industry.

System-Level ESD-Induced Voltage Fluctuation to the Power of Integrated Circuits on System Board

Based on the voltage and current waveforms, the mechanism of the system-level electrostatic-discharge (ESD) induced the voltage fluctuation to the power of integrated circuits (ICs) on system board is studied. When a contact discharge ESD test is performed at a connector pin, which is terminated with an I/O pin of an IC, not all the current from the system-level ESD may flow through the IC to the ground of the system board. So, the remaining currents can only flow through the power line of the ICs and the connection wire into the power supply to the ground. The power supply has the feedback and pulsewidth modulation circuits to regulate its output voltage. Therefore, the output current of the power supply will interact with the remnant current from the ICs on system board, resulting in the current flowing through the connection wire in the microelectronics system back and forth. Hence, the power of system board will be pulled up and down by the connection wire based on L·(dI/dt), since it acts as an inductor during the alternating current. With the voltage swinging up and down, the p-n junctions in the power domain seems to be driven into the avalanche breakdown or forwarded to generate a lot of electrons and holes inside the ICs, leading to the latch-up event at the low latch-up immunity region.

Research on ESD failure voltage model of the T-shaped wiring structure in GOA products

In the GOA (Gate on Array) circuits, which are commonly employed in LCD (Liquid Crystal Display) products, the metal wire layers have been found to be sensitive to ESD (Electrostatic Discharge) in production, leading to an increase in the failure rate of GOA products, especially in T-shaped wiring structures. In this paper, we conducted a study on the relationship between the ESD failure voltage and structure parameters of T-shaped wiring structures in GOA products to enhance their reliability. We established an ESD failure voltage model for T-shaped wiring structures based on the relevant electrical breakdown theory. And failure voltage and gap breakdown voltage data are required for accurate model parameters fitting. Hence, ESD tests on the T-shaped wiring structure samples were conducted. In addition, ESD simulation of T-shaped wiring structure using CST software was applied to supply gap voltage data unavailable from tests. Based on the results of the tests and simulation, parameters of the ESD failure voltage model were fitted. And we performed the model modification using verification tests for higher accuracy. The results show that our model errors are below 5 %. Guided by the ESD failure voltage model, a more reliable T-shaped structure can be produced in GOA.

Machine Learning Techniques for the Prediction of the Magnetic and Electric Field of Electrostatic Discharges

The magnetic and electric fields of electrostatic discharges are assessed using the Naïve Bayes algorithm, a machine learning technique. Laboratory data from electrostatic discharge generators were used for the implementation of this algorithm. The applied machine learning algorithm can be used to predict the radiated field knowing the discharge current. The results of the Naïve Bayes algorithm are compared to a previous software tool derived by Artificial Neural Networks, proving its better outcome. The Naïve Bayes algorithm has excellent performance on most classification tasks, despite its simplicity, and usually is more accurate than many sophisticated methods. The proposed algorithm can be used by laboratories that conduct electrostatic discharge tests on electronic equipment. It will be a useful software tool, since they will be able to predict the radiating electromagnetic field by simply measuring the discharge current from the electrostatic discharge generators.

Improvement of electrostatic discharge sensitivity of lead styphnate particles using some polymer coating agents

ABSTRACT This work is devoted to reducing the electrostatic discharge sensitivity of lead styphnate (LS) particles by using the microencapsulation technique involving the solvent/non-solvent method in which viton A and nitrocellulose are used as coating agents. Improvement in quality and sensitivity of LS particles were studied by using friction, impact, electrostatic discharge and flash point tests. Electrostatic discharge sensitivity results confirmed the better performance of samples coated with viton A compared to nitrocellulose. Based on the experimental results, the most desensitized lead styphnate particles were obtained by using 5% (w/w) of viton A as the coating agent and electrostatic discharge sensitivity increasing from 0.4 to 1 mJ.

Analysis of the ESD Reconstruction Methodology Based on Current Probe Measurements and Frequency Response Compensation for Different ESD Generators and Severity Test Levels

System-level electrostatic discharge testing according to IEC 61000-4-2 has been the main standardized electrostatic discharge immunity testing procedure for the last few decades. The correlation between a failed test result and the injected electrostatic discharge current waveform characteristics, as well as the reduced reproducibility of the standard methodology, have always concerned product manufacturers and test engineers. In an effort to accurately reconstruct the electrostatic discharge current during immunity testing, researchers are focusing more and more on the usability of current probes in capturing the injected current in “real time”. In this article, the results of a proposed methodology, based on current probe measurements and a frequency response compensation method, published in recent bibliography, for different test levels and electrostatic discharge generators are presented, aiming to highlight the advantages and disadvantages of the method, investigate its universal applicability, and introduce points of future work toward the current reconstruction during system-level electrostatic discharge testing effort.

Stacking-MOS Protection Design for Interface Circuits Against Cross-Domain CDM ESD Stresses

Electrostatic discharge (ESD) is still a challenging reliability issue for integrated circuits (ICs) in advanced CMOS technology. With the development of ICs toward system-on-chip (SoC) applications, it has been common to integrate multiple separated power domains into a single chip for power management or noise isolation considerations. Besides, the fabricated transistors with thinner gate oxide for high-speed operation cause the ICs more sensitive to charged-device model (CDM) ESD events, especially under cross-domain stresses. The traditional cross-domain CDM ESD protection would result in some restrictions on circuit applications or cause some performance degradation. Thus, a new protection design with stacking footer/header metal-oxide-semiconductor (MOS) structure against cross-domain CDM ESD stresses was proposed in this work and verified in 0.18-μm CMOS technology. The proposed design got higher ESD robustness under CDM and HBM (human body model) ESD tests. Moreover, the CDM robustness of different stacking-MOS protection designs was also investigated in detail.

Electrostatic Discharge Characteristics of SiGe Source/Drain PNN Tunnel FET

Gate-grounded tunnel field effect transistors (ggTFETs) are considered as basic electrostatic discharge (ESD) protection devices in TFET-integrated circuits. ESD test method of transmission line pulse is used to deeply analyze the current characteristics and working mechanism of Conventional TFET ESD impact. On this basis, a SiGe Source/Drain PNN (P+N+N+) tunnel field effect transistors (TFET) was proposed, which was simulated by Sentaurus technology computer aided design (TCAD) software. Simulation results showed that the trigger voltage of SiGe PNN TFET was 46.3% lower, and the failure current was 13.3% higher than Conventional TFET. After analyzing the simulation results, the parameters of the SiGe PNN TFET were optimized. The single current path of the SiGe PNN TFET was analyzed and explained in the case of gate grounding.

ESD Design Verification Aided by Mixed-Mode Multiple-Stimuli ESD Simulation

Electrostatic discharge (ESD) protection is a grand design challenge for complex ICs in advanced technologies. ESD simulation is indispensable to guide ESD protection designs. However, no existing ESD simulation methods may accurately predict ESD protection designs in a universal manner due to various inherent limitations. TCAD-based ESD simulation is very useful for ESD protection designs. Transmission line pulse (TLP) and very fast TLP (VFTLP) are widely used to evaluate human body model (HBM) and charged device model (CDM) ESD protection designs, which provide rich details for calibrating TCAD ESD simulation for design prediction and validation. Using various ESD protection devices fabricated in 28nm CMOS and 45nm SOI CMOS technologies, a comprehensive experimental and simulation study finds that the ESD stimuli used in TCAD ESD design simulation have profound impacts on many subtle ESD protection behaviors, particularly in comparison with ESD testing. This study cautions against over-interpretation of TCAD ESD simulation results, obtained using any specific ESD stimulus, attempting to accurately predict practical ESD protection designs. A mixed-mode multiple-stimuli ESD simulation method is therefore developed to address the ESD stimulus induced ESD performance variation, hence offering a technique to achieve ESD protection design prediction.

Non-Pad-Based in Situ In-Operando CDM ESD Protection Using Internally Distributed Network

Charged device model (CDM) electrostatic discharge (ESD) protection is an emerging design challenge to ICs at advanced technology nodes. It was recently reported that the traditional pad-based CDM ESD protection methods are fundamentally faulty, which causes uncertainties in CDM ESD protection designs, testing and failure analysis. Re-thinking of onchip CDM ESD protection becomes imperative for complex ICs implemented in advanced technologies. This paper reports a disruptive CDM ESD protection method utilizing non-pad-based internally-distributed ESD protection network as a robust in situ in-operando CDM ESD protection solution. The proposed internal-distributed CDM ESD protection mesh network can be realized using interposer or through-silicon-via (TSV) ESD protection structures to achieve local 3D CDM ESD protection via heterogeneous integration. The new concept was validated using an internal-CDM-protected oscillator IC implemented in a foundry 45nm silicon-on-insulator (SOI) technology.

Analyze Scalable Sudoku-Type DTSCR ESD Protection Array Structures in 22nm FDSOI

This paper reports the design and analysis of scalable Sudoku-type diode-triggered silicon-controlled rectifier (DTSCR) electrostatic discharge (ESD) protection structures fabricated in a foundry 22nm fully-depleted silicon-on-insulator (FDSOI) technology. 3D TCAD and ESD testing confirm that the Sudoku DTSCR ESD structures can dramatically improve the ESD area efficiency. Transmission line pulse (TLP) measurement shows a high ESD area efficiency of 6.47mA/mum2 for Sudoku-DTSCR, 64.6% improvement over traditional finger-DTSCR structure. A scalability model was derived as design guidelines for optimizing Sudoku DTSCR ESD protection array structures.

Research on ESD Protection of Ultra-High Voltage nLDMOS Devices by Super-Junction Engineering in the Drain-Side Drift Region

Electrostatic discharge (ESD) transient events can often damage semiconductor components. Therefore, the ultrahigh-voltage (UHV) circular n-channel lateral diffused metal-oxide-semiconductor transistor (nLDMOS) usually used in power electronics needs to have ESD self-protection capabilities. In this paper, the geometric parameters of 300-V and 200-V UHV circular nLDMOSs were modulated using different layouts at the drain side. The high-voltage p-well (HVPW) layer was used to form various super junctions (SJs) in the drift region. The modulations were classified as SJ length, SJ concentration-gradient thickness, HVPW ring-sector, and rotated SJ concentration gradient modulations in the drift region. Various HVPWs were used to produce several SJs in the drain drift region. According to the final measurement results, all modulation processes maintained the original physical characteristics of high breakdown voltage. Devices with the SJ length and SJ concentration-gradient thickness’s modulations provided the best ESD robustness. The ESD testing value of the human-body model (HBM) will increase with the increase of the SJ length and SJ thickness modulations. The HBM value increased from the 1500 V reference to 4000V (increased by 166.66%).