Electrostatic Discharge Protection Research Articles

A 5 mW 28 nm CMOS Low-Noise Amplifier with Transformer-Based Electrostatic Discharge Protection for 60 GHz Applications

This paper presents a low-power 60 GHz low-noise amplifier (LNA) designed for Gbit/s applications using 28 nm CMOS technology. The LNA exploits a single-stage pseudo-differential architecture with integrated input transformer for both electrostatic discharge (ESD) protection and simultaneous noise/impedance matching. An effective power-constrained design strategy is adopted to pursue the lowest current consumption at the minimum noise figure (NF), with the best tradeoff between gain and frequency bandwidth. The LNA, which has been designed to drive an on–off keying (OOK) demodulator, is operated at a supply voltage as low as 0.9 V and achieves a voltage gain of about 21 dB with a 3 dB bandwidth of 2 GHz around 60 GHz. Thanks to the proper impedance transformation at the 60 GHz input, the amplifier exhibits an NF of 6.3 dB, also including the input transformer loss with a very low power consumption of about 5 mW. The adoption of a single-stage topology also allows an excellent input 1 dB compression point (IP1dB) of −4.7 dBm. The input transformer guarantees up to 2 kV human body model (HBM) ESD protection.

Exploration of a Novel Electric-Fuse Device with a Simple Structure of Ni Metal on a SiO2 Dielectric for Electrostatic Discharge Protection under a Human Body Model.

On-chip electrostatic discharge (ESD) protection poses a challenge in the chip fabrication process. In this study, a novel electric fuse (E-fuse) device featuring a simple structure of Ni metal on a SiO2 dielectric for ESD protection was proposed, and the physical mechanism of its operation was investigated in detail. Experimental evaluations, utilizing transmission line pulse (TLP) testing and fusing performance analyses, reveal that the E-fuse, constructed with a Ni metal layer measuring 5 μm in width, 100 μm in length, and 5 nm in thickness, achieved a significant ESD protection voltage of 251 V (VHBM) and demonstrates low-voltage fusing at a bias voltage of 7 V. Compared to traditional ESD protection devices, the E-fuse boasts a smaller size and removability. To assess fusing performance, devices of varying sizes were tested using a fusing lifetime model. This study supports both theoretical and empirical evidence, enabling the adoption of cost-effective, straightforward E-fuse devices for ESD protection.

A Self-Biased Triggered Dual-Direction Silicon-Controlled Rectifier Device for Low Supply Voltage Application-Specific Integrated Circuit Electrostatic Discharge Protection

A direct bidirectional current discharge path between the input/output (I/O) and ground (GND) is essential for the robust protection of charging device models (CDM) in the tightly constrained design parameters of advanced low-voltage (LV) processes. Dual-direction silicon controlled rectifiers (DDSCRs) serve as ESD protection devices with high efficiency unit area discharge, enabling bidirectional electrostatic protection. However, the high trigger voltage of conventional DDSCR makes it unsuitable for ASICs used for the preamplification of biomedical signals, which only operate at low supply voltage. To address this issue, a self-biased triggered DDSCR (STDDSCR) structure is proposed to further reduce the trigger voltage. When the ESD pulse comes, the external RC trigger circuit controls the PMOS turn-on by self-bias, and the current release path is opened in advance to reduce the trigger voltage. As the ESD pulse voltage increases, the SCR loop opens to establish positive feedback and drain the amplified current. Additionally, the junction capacitance is decreased through high-resistance epitaxy and low-concentration P-well injection to further lower the trigger voltage. The simulation results of LTspice and TCAD respectively demonstrate that ESD devices can clamp transient high voltages earlier, with low parasitic capacitance and leakage current suitable for ESD protection of high-speed ports up to 1.5 V under normal operating conditions.

Modeling and Testing of ESD Protective Textiles

This article discusses the important issue of designing textiles for electrostatic discharge (ESD) protection. ESD protective textiles are used to prevent the failure of electronic circuits. They also safeguard human health and life in explosive environments. The textiles are usually made of woven, knitted, or nonwoven fabrics incorporating a grid or strips of conductive fibers within a base material made of cotton, polyester, or blends of these materials. Various testing standards have been developed to evaluate the suitability of textiles for ESD protection. One of the most widely used is the EN 1149-3 standard, which outlines procedures for recording charge decay plots. The procedure can be used to evaluate all types of textiles. This paper discusses models corresponding to the standard developed in the general-purpose COMSOL Multiphysics software. Using the advanced numerical methods of the software, it is possible to graphically present the phenomena occurring during the application of the standard procedure and to determine the influence of the grid and material parameters on the shape of the charge decay plots. Furthermore, this article compares charge decay plots and shielding effectiveness measured in an accredited laboratory with simulation results.

A Novel Battery-Supplied AFE EEG Circuit Capable of Muscle Movement Artifact Suppression

In this study, the fundamentals of electroencephalography signals, their categorization into frequency sub-bands, the circuitry used for their acquisition, and the impact of noise interference on signal acquisition are examined. Additionally, design specifications for medical-grade and research-grade EEG circuits and a comprehensive analysis of various analog front-end architectures for electroencephalograph (EEG) circuit design are presented. Three distinct selected case studies are examined in terms of comparative evaluation with generic EEG circuit design templates. Moreover, a novel one-channel battery-supplied EEG analog front-end circuit designed to address the requirements of usage protocols containing strong compound muscle movements is introduced. Furthermore, a realistic input signal generator circuit is proposed that models the human body and the electromagnetic interference from its surroundings. Experimental simulations are conducted in 50 Hz and 60 Hz electrical grid environments to evaluate the performance of the novel design. The results demonstrate the efficacy of the proposed system, particularly in terms of bandwidth, portability, Common Mode Rejection Ratio, gain, suppression of muscle movement artifacts, electrostatic discharge and leakage current protection. Conclusively, the novel design is cost-effective and suitable for both commercial and research single-channel EEG applications. It can be easily incorporated in Brain–Computer Interfaces and neurofeedback training systems.

Прогнозирование помех электростатического разряда в электронном устройстве с использованием искусственной нейронной сети

Electrostatic discharge is a dangerous source of natural electromagnetic interference to the operation of modern electronic devices. Although measures have been taken to reduce and remove electrostatic discharge from the operating area of electronic devices, the absence of such discharge cannot be guaranteed. Therefore, when designing modern electronic devices, it is necessary to take into account the possibility of such electrostatic discharges in advance and take protective measures. The article proposes a method for predicting the amplitude of interference in the communication line of an electronic device when exposed to an electrostatic discharge on its metal case. The technique is based on the use of an artificial neural network. The technique includes the analysis of significant input parameters that affect the amount of interference in an electronic device; development of an experimental stand for measuring interference; choosing the structure and parameters of a neural network for predicting interference; choosing a training method for an artificial neural network; choosing a metric for assessing the quality of training; normalization of training data; training an artificial neural network using experimental noise data; predicting the amplitude of interference in the communication line of an electronic device when exposed to an electrostatic discharge on its body; where necessary, selecting and implementing electrostatic discharge protection measures. Examples of training an artificial neural network based on experimental data are given. The training was carried out for 572 epochs. For the training and testing sets, the discrepancy between the predicted data and the average measured noise values was 3.61% and 3.95%, respectively. Examples are given of predicting the amplitude of interference when exposed to electrostatic discharge. The results obtained indicate the possibility of practical use of an artificial neural network to solve problems of electromagnetic interference analysis.

Design of High-Reliability Low-Dropout Regulator Combined with Silicon Controlled Rectifier-Based Electrostatic Discharge Protection Circuit Using Dynamic Dual Buffer

Overshoot and undershoot caused by the current load impact the accuracy of the required output voltage and circuit performance. The transient response issue in existing low-dropout (LDO) regulators is a dynamic specification that must be addressed at the design stage. This transient response is influenced by system parameters such as stability and gain. The LDO regulator suggested in this study is designed to minimize the change in output voltage by considerably enhancing the gain using a dynamic dual buffer structure. A dynamic dual buffer is utilized to effectively control undershoot and overshoot. Under the conditions that the input voltage range is from 3.3 to 4.5 V, the maximum load current is 300 mA, the output voltage is 3 V, and the output of the proposed LDO regulator with the dynamic dual buffer structure has undershoot and overshoot voltages of 41 mV and 31 mV, respectively. That is, the output voltage of the proposed LDO regulator effectively provided and discharged an additional current suited for the undershoot/overshoot conditions to enhance the transient response characteristics. Furthermore, the electrostatic discharge (ESD) robustness characteristics of the proposed LDO regulator improved because of the silicon-controlled rectifier underlying the ESD protection device embedded in the output node and power line.

Strong and antistatic biomass adhesive for wood-based composites with electrostatic discharge protection function

Soybean protein adhesive, as an aldehyde-free biomass adhesive, has gained significant attention as an environmentally friendly material in recent years. It not only aligns with the objectives of the double carbon strategy but also contributes to the environmental protection strategy of reducing carbon emissions. And the functional modification of soybean protein adhesive and its wood composite hold great importance in expanding its application domains and meeting specialized requirements. This research focused on developing a robust, antistatic adhesive derived from soy protein as an alternative to formaldehyde-based resins, which represents a critical path in the advancement of wood-based composites that are free from formaldehyde and possess functional properties. However, ensuring the bonding strength of soy protein adhesive while developing antistatic adhesives and their wood-based composite materials is of great research value and challenge. Inspired by the organic-inorganic hybrid structure, this study aimed to prepare a strong and durable soy protein adhesive with excellent mechanical strength and multifunctionality by using a self-synthesized crosslinking agent called AP and the loaded two-dimensional MXene, which was stabilized in a dispersion of nanocellulose (CNC). The dry and wet shear strength of the resulting adhesive increased by 103.8 % and 113.8 % to 2.21 MPa and 1.24 MPa, indicating the stable crosslinking structure formed in adhesive system by the covalent bond between self-synthesized crosslinking agent AP and the carboxyl groups on proteins, as well as the hydrogen bond interactions between C-M and the proteins. Furthermore, the adhesive exhibited significant antistatic and self-extinguishing properties, with the particleboard modified by adhesive SPI/C-M/AP having a resistivity of 9.212 × 1011 Ω cm. The resistivity decreased with increasing MXene content, providing potential applications for places such as school computer rooms and factory electronic equipment rooms. This breakthrough in multifunctional biomass-based adhesives and composite materials enriches the preparation of new types of biomaterials with antistatic and flame retardant properties.

Challenges: ESD Protection for Heterogeneously Integrated SoICs in Advanced Packaging

Electrostatic discharge (ESD) failure is a major reliability problem for all forms of microelectronics products. ESD protection is required for all integrated circuits (ICs). As dimension scaling-down approaches its physical limit, heterogeneous integration (HI) emerges as a main pathway towards the age beyond Moore’s Law to facilitate advanced microsystem chips with extreme performance and rich functionalities. Advanced packaging is a key requirement for HI-enabled integrated systems-on-chiplets (SoIC) that require robust ESD protection solutions. This article outlines key emerging technical challenges associated with smart future SoIC microsystem superchips in the context of advanced packaging technologies.

Investigation on MOS shunt LVTSCR for ESD application

Continuously scaling down ICs result in more stringent electrostatic discharge (ESD) protection design requirements. Compared with other devices, silicon-controlled rectifier (SCR) has become the first choice for its area efficiency and robustness. In order to improve the latch-up issue of SCR, various schemes have been proposed. A simple method is to extend the SCR path length, which will result in the enlarged ON resistance. Segment technology is also used to improve the holding voltage of SCR, but it will shrink the effective emitter area and lead to the serious degradation of ESD robustness. MS-LVTSCR is used to protect CMOS input ports. The circuit operating voltage is 3.3V and the gate oxide DC breakdown voltage is 19V so that considering the safety margin, the ESD window is from 3.63V to 17.1V. This work proposes a novel MOS shunt low-voltage trigger silicon-controlled rectifier (MS-LVTSCR) electrostatic discharge protection device by inserting an embedded PMOS structure. Compared with the conventional LVTSCR, the proposed MS-LVTSCR achieves 53% improvement in the holding voltage and still maintains high ESD robustness with a current level of 31.5 mA/μm without more device area consumption. In addition, both the TCAD simulation and theoretical analysis were carried out to explore the principle of current shunt effect to improve holding voltage. The extra shunt paths will weaken the conductance modulation effect of the main drift region in the main SCR path and its holding voltage can be further raised by reducing the proportion of main drift region current in the total current. We also conducted detailed studies on the mechanisms and geometry effects of this newly proposed structure via experimental validations.

Design of a LVTSCR triggered SCR device for low voltage ESD protection

In this paper, a novel silicon-controlled rectifier (SCR) electrostatic discharge (ESD) protection device, called low voltage triggered SCR (LVTSCR) triggered SCR (LVTSCRTSCR), is proposed for 3.3 V I/O protection applications in 0.18 μm CMOS technology. One side of the device is the traditional LVTSCR structure, and other side is the traditional SCR structure. The two structures are connected by a floating P+ diffusion layer. The working principle of LVTSCRTSCR was verified by the TCAD simulation results and TLP test results. The test results show that the triggering voltage of LVTSCRTSCR is determined by the traditional LVTSCR, with a value of 9.850 V. The holding voltage of the device can be effectively improved by increasing the size of the floating diffusion layer D4. When D4 = 6 μm, the holding voltage can be 4.491 V, suitable for 3.3 V I/O.

Highly flexible porous indium-tin-oxide coating with enhanced atomic oxygen and electrostatic discharge resistance

Polyimides (PI) are commonly used in spacecraft in low Earth orbit (LEO) due to their flexibility. However, they are susceptible to erosion caused by atomic oxygen (AO) and electrostatic discharge (ESD) induced by plasma in the harsh LEO environment. Indium-tin-oxide (ITO), owing to its excellent electrostatic and AO resistance, has emerged as the most promising inorganic protective coating for PI in LEO applications. But the inherent rigidity of ITO and the high-temperature annealing process commonly required for synthesis make it challenging to employ ITO as flexible polymer substrates. In this work, we have synthesized the porous ITO layer with a low-temperature (≤150 °C) method and combined it with layer double hydroxides (LDHs) to enhance the flexibility, AO resistance, and ESD protection of the coating. The porous ITO in combination with LDHs layers effectively improve the flexibility (after 20,000 bending cycles without failure problem), AO resistance (erosion yield down to -0.102 × 10−26 cm3/atom under an exposure dose of 5.22 × 1021 atoms/cm2) and ESD resistance properties (sheet resistance around 202 kΩ/sq). The synthesis method proposed avoids the high-temperature annealing and the residual stress effect on the coating's flexibility. This work provides an efficient approach to realizing flexible and protective coating on polymers for long-lasting spacecraft electronic devices in low Earth orbit.

Ferroelectric Domain Wall Delayer and Low-Dropout Regulator.

A switching-type power converter providing an accurate and stable switching output voltage against line/load variations and power supply ripple is mostly complicated in system-on-chip power management integrated circuits (PMICs) within a limited occupation area. Here we fabricated domain wall (DW) nanodevices using an X-cut LiNbO3 thin film on silicon. The domain switching event occurs after a delay time predicted by Merz's law under the applied voltage. But the output current is irrespective of the applied voltage and can be adjusted by conducting wall width as well as input resistance in the circuit. The regulating currents appear repetitively across the volatile interfacial domains between the nanodevice and electrode under intermittently applied voltages. A wall-current-limited domain switching model is developed to explain the phenomenon. The multifunctional DW nanodevices with smaller occupation areas can serve as compact low-dropout regulators in PMICs, time-domain delayers in energy-efficient neural network systems, and on-chip electrostatic discharge protection besides nonvolatile memories and selectors.

Characteristic parameter model and circuit‐level simulation of gate‐controlled dual direction SCR for on‐chip ESD protection

SummaryDual‐directional SCR (DDSCR) with bidirectional discharge paths and high robustness is widely employed for electrostatic discharge (ESD) protection in integrated circuits. However, the design and simulation of on‐chip ESD protection circuits for dual‐directional paths remain challenging due to a lack of relevant device models. This paper designs a Gate‐Controlled Dual‐Direction SCR (GDDSCR) for providing electrostatic discharge (ESD) protection in industry‐level temperature sensors. Furthermore, a new behavioral model is developed based on the GDDSCR for simulating ESD protection circuits along both forward and reverse paths. Experimental results demonstrate that the GDDSCR behavioral model accurately reproduces the IV characteristics observed in bidirectional transmission line pulse (TLP) tests. In addition, the equivalent circuit based on human body model (HBM) is used for transient simulation, and the accuracy of the model is verified by relevant HBM experiments. The proposed model allows the direct extraction of parameters such as trigger voltage (Vt1), holding voltage (Vh), and on‐state resistance (Ron) through TLP testing, facilitating easy application to other types of DDSCR devices.

Wafer-Scale Carbon Nanotubes Diodes Based on Dielectric-Induced Electrostatic Doping.

Diodes based on p-n junctions are fundamental building blocks for numerous circuits, including rectifiers, photovoltaic cells, light-emitting diodes (LEDs), and photodetectors. However, conventional doping techniques to form p- or n-type semiconductors introduce impurities that lead to Coulomb scattering. When it comes to low-dimensional materials, controllable and stable doping is challenging due to the feature of atomic thickness. Here, by selectively depositing dielectric layers of Y2O3 and AlN, direct formation of wafer-scale carbon-nanotube (CNT) diodes are demonstrated with high yield and spatial controllability. It is found that the oxygen interstitials in Y2O3, and the oxygen vacancy together with Al-Al bond in AlN/Y2O3 electrostatically modulate the intrinsic CNTs channel, which leads to p- and n-type conductance, respectively. These CNTs diodes exhibit a high rectification ratio (>104) and gate-tunable rectification behavior. Based on these results, we demonstrate the applicability of the diodes in electrostatic discharge (ESD) protection and photodetection.

Organosilicon elastomers of MWCNTs and nano-sized metals for heating purposes

Silicone elastomers are continuously gaining importance in a variety of industrial applications, including strain gauges, electrical heaters, electromagnetic interference, and electrostatic discharge protection coatings. But these materials have certain drawbacks such as high cost, poor resistance to solvents, low tear strength, limited high-temperature resistance, difficulty in bonding and limited abrasion resistance. Therefore, unique nanocomposites of organosilicon elastomers with metals have been prepared using MWCNTs. The prepared nanocomposites demonstrated nano-diameter structures (15–60 nm) with micron-sized fibrous structures (12–60 μm). Aluminum elongated inclusions (60 µm in size) and bronze spherical inclusions (12–30 µm) were observed in the nanocomposites. The composites containing MWCNTs, Co-Mo/Al2O3-MgO catalyst and bronze (3 wt. %) had the maximum thermal and electrical conductivity. The prepared nanocomposites were used to make the heaters. The heating of the heaters was carried out by applying a voltage of 12–24 V. The Highest temperature achieved was more than 50 °C in all the heaters. By supplying 12–24 V electricity to the heaters in the ventilation and heat recirculation system, the interior of a minibus or living space can be heated. The developed electric heater has another important economic application in temperature-controlled materials.

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Electrostatic discharge (ESD) and electromigration are critical issues that significantly impact the reliability of ICs. While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

A novel low trigger voltage low leakage SCR for low-voltage ESD protection

Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 °C is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.

Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip

The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic bipolar junction transistors (BJTs) for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1 ), a 96.1% improvement in holding voltage (Vh ), and achieves an equivalent human body model protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.

Establishment of analytical model for electrostatic discharge gate-to-source capacitance of power metal-oxide-semiconductor field-effect transistor

In the actual human body model (HBM) test, it is found that the electrostatic discharge (ESD) test results of various power metal-oxide-semiconductor field-effect transistor (MOSFET) devices show asymmetry between forward withstand voltage and reverse withstand voltage, while the ESD process does not distinguish between positive direction and negative direction. Large differences between forward and reverse withstand voltages are unacceptable for power MOSFETs or as ESD protection devices. The problem of its causing device failure is particularly pronounced. In this work, by establishing the analytical model of gate-to-source capacitance of SGT-MOSFET, VUMOSFET and VDMOS under the forward and reverse voltages, we comparatively analyze the reasons for the asymmetry of the forward and reverse withstand voltages and their different ratios of the three kinds of power MOSFETs, which provides a theoretical basis for testing the device’s ESD and the analyzing their reliability. It is found that the ESD forward and reverse withstand voltage asymmetry phenomena of different power MOSFET structures are related to the variation of gate-to-source capacitance, caused by the reverse-type layer. When a forward voltage is applied across the gate and source, the device gate-to-source capacitance consists of the oxide layer capacitance around the gate in parallel; when a reverse voltage is applied, the gate-to-source capacitance consists of the virtual gate-to-drain capacitance in series with the inverse layer capacitance and then in parallel with the other oxide layer capacitance around the gate. This results in a decrease of the gate-to-source capacitance at the reverse voltage, making the device reverse withstand voltage greater than the forward withstand voltage. The difference in the ratio of ESD reverse withstand voltage to forward withstand voltage among different devices is related to the change of the capacitance of the inverse layer in the gate-to-source capacitor under reverse voltage caused by the difference in device structure.