Electrostatic Discharge Protection Research Articles

Design of current detection LDO regulator with silicon controlled rectifier based electrostatic discharge protection circuit to provide optimized voltage and power for system‐on‐chip applications

Various levels of circuits and systems in the ultra-low nanometer fabrication process should be considered to implement a system-on-chip (SOC) application to reduce power consumption. This letter is intended to propose a current detection structure that supplies and discharges additional current along the load current to provide the optimized voltage and power for SOC applications. The proposed electrostatic discharge (ESD) protection circuit placed on the power line and I/O has improved the reliability by preventing the direct or indirect destruction of the internal integrated circuit (IC) due to ESD. In addition, the proposed low drop out (LDO) regulator for the low-voltage applications has combined an ESD protection circuit to secure the high reliability of the IC. The proposed LDO regulator is implemented with a 0.18-μm BCD process and is kept an undershoot voltage of 23 mV and an overshoot voltage of 25 mV for a load current of 200 mA.

Selective Overview of 3D Heterogeneity in CMOS.

As the demands for improved performance of integrated circuit (IC) chips continue to increase, while technology scaling driven by Moore’s law is becoming extremely challenging, if not impractical or impossible, heterogeneous integration (HI) emerges as an attractive pathway to further enhance performance of Si-based complementary metal-oxide-semiconductor (CMOS) chips. The underlying basis for using HI technologies and structures is that IC performance goes well beyond classic logic functions; rather, functionalities and complexity of smart chips span across the full information chain, including signal sensing, conditioning, processing, storage, computing, communication, control, and actuation, which are required to facilitate comprehensive human–world interactions. Therefore, HI technologies can bring in more function diversifications to make system chips smarter within acceptable design constraints, including costs. Over the past two decades or so, a large number of HI technologies have been explored to increase heterogeneities in materials, technologies, devices, circuits, and system architectures, making it practically impossible to provide one single comprehensive review of everything in the field in one paper. This article chooses to offer a topical overview of selected HI structures that have been validated in CMOS platforms, including a stacked-via vertical magnetic-cored inductor structure in CMOSs, a metal wall structure in the back end of line (BEOL) of CMOSs to suppress global flying noises, an above-IC graphene nano-electromechanical system (NEMS) switch and nano-crossbar array electrostatic discharge (ESD) protection structure, and graphene ESD interconnects.

An On-Chip ESD Sensor for Use in Advanced Packaging

Electrostatic discharge (ESD) failure results in about 35% of integrated circuit (IC) field return and causes several billion-dollar losses to the semiconductor industry per year. Most modern ICs include on-chip ESD protection circuitry which comes at the cost of I/O performance. Static charge accumulation during transport and handling may exceed the limits of this ESD protection and cause damage to the ICs. Modern advanced packaging technologies are not amenable to rework if one or more components are ESD compromised. An on-chip ESD sensor is useful in identifying and preventing the assembly of ESD compromised dielets in any advanced packaging technology. Two approaches for on-chip ESD sensor that can be employed on any die, following the ground rules within that technology are presented. Both approaches are designed, simulated, fabricated, and experimentally characterized using GlobalFoundries 22-nm fully depleted silicon-on-insulator (FDSOI) technology. While determining ESD voltage using sensors, we encounter two events that are naturally random. First, ESD is a random event with some probability distribution function (PDF) with respect to voltage. In addition, oxide breakdown within the ESD sensors is also random with a Weibull distribution. A Bayesian method is developed for the estimation of ESD voltage PDF using sensors. Experimental testing of the sensors using an ESD gun and ESD voltage estimation from the number of sensors that broke down is presented. The estimated ESD voltage closely matches the ESD voltage that the dies were subjected to during experimental verification.

Enhancement of holding voltage by a modified low-voltage trigger silicon-controlled rectifier structure for electrostatic discharge protection

A novel structure of low-voltage trigger silicon-controlled rectifiers (LVTSCRs) with low trigger voltage and high holding voltage is proposed for electrostatic discharge (ESD) protection. The proposed ESD protection device possesses an ESD implant and a floating structure. This improvement enhances the current discharge capability of the gate-grounded NMOS and weakens the current gain of the silicon-controlled rectifier current path. According to the simulation results, the proposed device retains a low trigger voltage characteristic of LVTSCRs and simultaneously increases the holding voltage to 5.53 V, providing an effective way to meet the ESD protection requirement of the 5 V CMOS process.

A Dielectric Polymer/Metal Oxide Nanowire Composite for Self-Adaptive Charge Release.

Electrostatic discharge is a fatal threat to a variety of electronic products. Here we report on a polymer nanocomposite composed of a dielectric polymer embedded with aligned core-shell structured nanowires for highly efficient distributed electrostatic discharge protection. The dielectric nanocomposite is capable of self-adaptive charge release, stemming from the nonlinear interface built in the Bi/Co oxide coated ZnO nanowires that leads to a "hand-in-hand" double-Schottky barrier. The ultralow filler concentration (e.g., 0.5 vol %) endows the nanocomposite with low permittivity (close to the pristine polymer matrix) and high optical transmittance (75%) in the visible light wavelength range, which is desirable in packaging materials and display coatings for portable electronics. The effectiveness for electrostatic discharge protection was validated with an organic light-emitting diode screen protected by the nanocomposite that survived multiple rounds of electrostatic discharge.

All-HKMG-bounded SCR for advanced ESD protection in 14 nm FinFET technology

In this paper, a novel all-high-K metal gate (HKMG)-bounded silicon-controlled rectifier (AHBSCR) is proposed for advanced electrostatic discharge (ESD) protection in FinFET processes. Depart from its prior arts, in AHBSCR, both the main SCR path and the triggering diode path are placed along the Fin direction, and all active areas are bounded by HKMG, thus expressing superior conduction capability under various ESD stresses and a more compact silicon footprint. Experimental results show that the proposed AHBSCR owns a suitable snapback window of 1.1 V–1.6 V, a fast turn-on speed of only 400 ps, an extreme low leakage current of less than 100 pA@-1 V as well as a figure of merit of 24.3 mA fF−1, indicating it is competent to replace the conventional FinFET diodes in rail-based ESD network to further improve the efficiency of ESD protection.

A Millimeter-Wave Broadband Reflectionless ESD Protection Device

In this letter, a broadband millimeter-wave (mm-wave) electrostatic discharge (ESD) protection structure is proposed and verified in a 40-nm CMOS process. The main ESD protection device is a diode-triggered silicon-controlled rectifier (DTSCR) with a tunable trigger voltage. Two weakly-coupled inductors are embedded to increase the operating bandwidth. Both theoretical analysis and simulation results show that a low coupling factor is necessary to obtain the wideband characteristic. The proposed design exhibits good ESD protection performance (HBM robustness >1.875kV), fast turn-on speed, wideband reflectionless characteristic (S11<–15dB within 33.6-50GHz), tunable trigger voltage and low leakage current. Therefore, this new device is suitable for ESD protection of input/output (I/O) pads in mm-wave-communication applications.

Silicon-Controlled Rectifier Embedded Diode for 7 nm FinFET Process Electrostatic Discharge Protection.

A new silicon-controlled rectifier embedded diode (SCR-D) for 7 nm bulk FinFET process electrostatic discharge (ESD) protection applications is proposed. The transmission line pulse (TLP) results show that the proposed device has a low turn-on voltage of 1.77 V. Compared with conventional SCR and diode string, the proposed SCR-D has an additional conduction path constituting by two additional inherent diodes, which results in a 1.8-to-2.2-times current surge capability as compared with the simple diode string and conventional SCR with the same size. The results show that the proposed device meets the 7 nm FinFET process ESD design window and has already been applied in actual circuits.

A Novel Voltage Divider Trigger SCR With Low Leakage Current for Low-Voltage ESD Application

In this article, a novel voltage divider trigger silicon-controlled rectifier (VDTSCR) with low trigger voltage and low leakage current for electrostatic discharge (ESD) protection applications has been proposed and verified in a 65-nm epitaxial CMOS process. The trigger structure formed by a voltage divider and an nMOS is introduced to the proposed structure. The voltage divider composed of two series capacitors can control the turn-on of the nMOS, and the nMOS current can trigger the silicon-controlled rectifier (SCR) device to reduce the trigger voltage of the proposed device. Such triggering structure is fully embedded in the proposed device for saving area. The measurement results show that the proposed device can achieve a low trigger voltage of 2.88 V, a low leakage current of 120 pA, and the second breakdown current of 4.35 A for a 1.2-V application. Furthermore, the VDTSCR device can be immune from the risk of latch-up and false triggering. Due to the low trigger voltage and low leakage current of the proposed device, it is suitable for low-voltage and low-power applications.

Design and Analysis of a 140-GHz T/R Front-End Module in 22-nm FD-SOI CMOS

This article presents novel methodologies and practical design considerations for a <inline-formula> <tex-math notation="LaTeX">$D$ </tex-math></inline-formula>-band transmit/receive (T/R) front-end module (FEM) in 22-nm fully depleted silicon-on-insulator (FD-SOI/FDX) CMOS technology for beyond-5G wireless communication. An ABCD-matrix-based synthesis methodology is proposed to co-design the T/R switch (SW) topology, including the power amplifier (PA) output and the low noise amplifier (LNA) input matching networks, to minimize the losses in both Tx and Rx modes. Based on this synthesis, an asymmetric T/R SW topology is realized with intrinsic electrostatic discharge (ESD) protection. Both the stacked-field-effect transistor (FET) PA and LNA adopt differential topologies with transformer-based matching networks to eliminate unwanted effects from common-mode parasitics. Passive gain-boosting techniques are used for both PA and LNA to enhance different TRx specifications. A reusable unit-cell layout strategy is applied for transistor arrays to accelerate the multiple-stage PA implementation and maintain uniform performance and minimal parasitics. At 140 GHz, the Tx achieves a power gain <inline-formula> <tex-math notation="LaTeX">$G_{p}$ </tex-math></inline-formula> of 33.6/35.7 dB, a saturated output power <inline-formula> <tex-math notation="LaTeX">$P_{\mathrm{ sat}}$ </tex-math></inline-formula> of 12.5/14.7 dBm, a peak power-added efficiency (PAE) of 10.8/11.3&#x0025;, and an output 1-dB compression point (OP1dB) of 9.4/11.2 dBm with nominal/boosted supplies. An average output power (<inline-formula> <tex-math notation="LaTeX">${P_{out}}_{avg}$ </tex-math></inline-formula>)/PAE of 4.9 dBm/2&#x0025; is obtained for a 4-GHz bandwidth 64-QAM single-carrier signal at an error-vector magnitude (EVM) of &#x2212;24.8 dB. Moreover, its Tx-mode reliability has been assessed. At 140 GHz, the Rx achieves a 20-dB <inline-formula> <tex-math notation="LaTeX">$G_{p}$ </tex-math></inline-formula>, a &#x2212;24-dBm input 1-dB compression point (IP1dB), and a 9.2-dB noise figure (NF) with only 20-mW power consumption from a 0.8-V supply. This compact FEM has a PA/LNA core area of 0.024/0.032 mm², respectively.

Power Rail ESD Protection Design Methodology Using Voltage-Gain Inverter Based Feedback Technology

In power rail, electrostatic discharge (ESD) is one of the assured issues to be faced. This paper intended to have a voltage gain inverter-based response technology for power rail ESD protection. This paper proposes a power MOSFET to discharge ESD current with 10 ns RC time constant for triggering and transmission gate based clamp is to keep it on until ESD event, which is 28% more efficient than the conventional clamp. The proposed clamp can endure 4500V of HBM (Human Body Model) pulse and also suitable for Charged-Device Model (CDM) protection. Here, LTspice software is used to check out the ESD performance of the transmission gate-based clamp.

Electrostatic pull-in application in flexible devices: A review

The electrostatic pull-in effect is a common phenomenon and a key parameter in the design of microscale and nanoscale devices. Flexible electronic devices based on the pull-in effect have attracted increasing attention due to their unique ductility. This review summarizes nanoelectromechanical switches made by flexible materials and classifies and discusses their applications in, among others, radio frequency systems, microfluidic systems, and electrostatic discharge protection. It is supposed to give researchers a more comprehensive understanding of the pull-in phenomenon and the development of its applications. Also, the review is meant to provide a reference for engineers to design and optimize devices.

CMOS Interface Circuits for High-Voltage Automotive Signals

The acquisition of high-voltage signals from sensors and actuators in an internal-combustion engine is often required for diagnostic purposes or in the case of conversion to alternative fuels, such as hydrogen, natural gas, or biogas. The integration of electronic interfaces and acquisition circuits in a single device provides benefits in terms of component-count reduction and performance. Nonetheless, the high voltage level of the involved signals makes on-chip design challenging. Additionally, the circuits should be compatible with the CMOS technology, with limited use of high-voltage options and a minimum number of off-chip components. This paper describes the design and the implementation in 350 nm CMOS technology of electronic interfaces and acquisition circuits for typical high-voltage signals of automotive context. In particular, a novel co-design of dedicated voltage clamps with electro-static discharge (ESD) protections is described. The proposed circuits require only a single off-chip resistor, and they are suitable for the acquisition of signals with peak voltages up to 400 V. The measured performance of the silicon prototypes, in the [−40 °C, +125 °C] temperature range, make the proposed electronic interfaces suitable for the automotive domain.

SI Considerations in Flexible Channels on High-Speed Intra-Panel Interface for Large-Size Flat Panel Display Applications

In flat panel display modules with a large-size and high-resolution for TV applications, signaling channels are relatively short on flexible printed circuit (FPC) cable or chip-on-film (COF) package when compared to those of the source PCBs. However, the short distance channels can significantly affect overall signal integrity (SI) performance. Thus, this letter focuses mainly on analysis and design of signal interconnection on FPC cable and COF package in terms of impedance matching and crosstalk. By optimizing the FPC cable design to mitigate crosstalk as well as insertion loss, the opening area of eye diagram was found to be improved more than twice over the previous one. In addition, through adjusting process of on-die capacitance of electro-static discharge (ESD) protection circuitry in the input stage of a high-speed circuit block, the created parasitic inductance of COF package trace was observed to be compensated. This optimization process can improve greatly system performance by widening the input eye opening. Finally, we propose channel design considerations and design guidelines to ensure better SI performance in flexible channels on high-speed intra-panel interface for large-size liquid crystal display (LCD) TV applications.

A Scalable Model for Snapback Characteristics of Circuit-Level ESD Simulation

It is challenging to simulate the snapback behaviors under electrostatic discharge (ESD) stresses due to the limitation of simulation program with integrated circuit emphasis (SPICE) simulation tools. In this paper, a new model is proposed to investigate the avalanche breakdown effect using the voltage-controlled current source (VCCS), which greatly facilitates the calculation of the avalanche multiplication factor M and improves the convergence characteristics. In particular, this new method transfers the exponential relationship of M into the linear relationship of the VCCS gain. The versatility of the model is validated by its operations in various ESD protection circuits with MOS as the discharge device, while the scalability is demonstrated by its applications in varied device sizes.

Design and optimization of DTSCR for high-speed I/O ESD protection of on-chip ICs

A gate-assisted and diode-triggered silicon controlled rectifier with the waffle layout (GDTSCR-WL) is proposed and investigated. By designing the waffle layout in the conventional diode-triggered silicon controlled rectifier (DTSCR), the electrostatic discharge (ESD) performance of the GDTSCR-WL can be used to optimize remarkably, especially for the parasitic capacitance, clamping voltage (V C), and current handling ability. By further introducing the gate-assisted trigger effect, the GDTSCR-WL can discharge the ESD-induced current more quickly. The technology computer aided design (TCAD) simulations and electrical test results indicate that the GDTSCR-WL has extraordinary ESD performance, such as a V C of 1.24 V, a turn-on resistance of 0.14 Ω, and the large figure of merit of 5.76 mA μm−2, outperforming dual-diode string and DTSCR. Moreover, by adjusting the width W 1 and space W 2 of diode blocks with the waffle layout, the capacitance of the GDTSCR-WL can be continuously decreased from 140 to 92 fF. The optimized GDTSCR-WL with a small capacitance can pass the 8 kV human body model test, providing an efficient and optional solution for high-speed input/output ESD protection of on-chip ICs.

The ESD Characteristics of a pMOS-Triggered Bidirectional SCR in SOI BCD Technology

In this work, the electrostatic discharge (ESD) characteristics of a pMOS-triggered bidirectional silicon-controlled rectifier (PTBSCR) that was fabricated in a 0.18 μm silicon-on-insulator (SOI) bipolar-CMOS-DMOS (BCD) process, is investigated. The multi-snapback phenomenon was observed under the transmission line pulsing (TLP) test system. It was found that gate voltage and inserting shallow trench isolation (STI) can significantly affect the trigger voltage and holding voltage. The underlying physical mechanism related to the multi-snapback phenomenon and the effects of gate voltage on the critical parameters was investigated through the experimental results and the assistance of technology computer-aided design (TCAD) simulations. The adjustments of gate voltage and STI on the critical ESD parameters of the device provide an effective design idea for low-voltage ESD protection in the SOI BCD process.

Frequency Based Method Investigation to Extract an ESD Protection Dynamic SPICE Model From TLP Measurement

In order to ensure reliability of systems early in the design phase, it is becoming crucial to have models able to predict the behaviors of systems exposed to electrostatic discharge (ESD). This is an increased necessity since the number of embedded electronic products is growing and since they are involved in applications where people&#x0027;s safety is a requirement. Until now, quasi-static models of protection devices have succeeded in providing fairly good results in failure predictions (mainly hard failures). Today, the increased frequency range of the devices requires dynamic models able to reproduce its transient behavior. In this article, we investigate if conventional modeling methods of linear devices, generally used in frequency domain, could be used to get an equivalent frequency model for ESD protection devices, which exhibit a nonlinear behavior. A methodology to extract an ESD protection SPICE model from transmission line pulse (TLP) measurements to address transient and frequency simulation is proposed and detailed. We will demonstrate that in well-defined conditions, such frequency models can give accurate results to predict overshoots related to protection devices triggering delays. Validation of the models is performed under TLP and human metal model conditions on three off-the-shelf devices.

Robust Silicon-Controlled Rectifier With High-Holding Voltage for On-Chip Electrostatic Protection

In this article, a robust high-holding voltage silicon-controlled rectifier (HHSCR) is implemented and realized in a 0.18-<inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> BCD process for on-chip electrostatic discharge (ESD) protection. The proposed HHSCR was constructed by embedding a NMOSFET in the p-well of a modified lateral silicon-controlled rectifier (MLSCR). Benefiting from the shunting effect of the embedded NMOSFET path, the proposed HHSCR achieved a high-holding voltage with a relatively high robustness. Transmission line pulse (TLP) test results show that the proposed HHSCR exhibits a high-holding voltage of 11.6 V and a failure current (<inline-formula> <tex-math notation="LaTeX">${I}_{\text {t2}}{)}$ </tex-math></inline-formula> of 1.59 A at a finger width of 50 <inline-formula> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula>. Furthermore, the internal physical mechanism of the proposed HHSCR was explored by technology computer-aided design (TCAD) simulation.

Novel ESD device design for STT-MRAM memory chip

An investigation of the influence of the magnetic field induced by electrostatic discharge (ESD) current on magnetic tunnel junction (MTJ) device is presented in the paper. The transient magnetic field generated by the ESD current is not considered in the traditional CMOS ESD protection strategy, which may be a reason of the degradation of the performance and the robustness of STT-MRAM. An ESD protection circuit of STT-MRAM is proposed in the paper, including the diode-based ESD devices, the filter circuit and the power clamp. Based on the waveform analysis of the three ESD standard test models, including HBM, MM and CDM, a filter circuit is added in the ESD device to decrease the influence of the high frequency components on the magnetic device. The diode-based ESD devices are integrated in the ESD structure, which is used for the ESD window of STT-MRAM for its low operating voltage. Based on the operation mechanism of the STT-MRAM, its ESD window allows a low operating voltage, thus the diode-based devices are chosen to be integrated in the ESD device. The distribution and magnitude of the magnetic field are studied in the paper. The results show that the ESD protection circuit of STT-MRAM can effectively suppress the magnetic field generated by the ESD current, hence increasing the stability of STT-MRAM. Under the influence of the HBM, MM and CDM events, the ESD disturbance probability of the MTJ device are 2.0 × 10−12, 5.8 × 10−9 and 1.1 × 10−12 respectively. The influence of the memory density and the distance between pads and memory array are also investigated in this paper. The ESD protection strategy proposed in the paper can be adopted for the future high performance STT-MRAM.