Abstract
Electrostatic discharge (ESD) failure is a major reliability problem for all forms of microelectronics products. ESD protection is required for all integrated circuits (ICs). As dimension scaling-down approaches its physical limit, heterogeneous integration (HI) emerges as a main pathway towards the age beyond Moore’s Law to facilitate advanced microsystem chips with extreme performance and rich functionalities. Advanced packaging is a key requirement for HI-enabled integrated systems-on-chiplets (SoIC) that require robust ESD protection solutions. This article outlines key emerging technical challenges associated with smart future SoIC microsystem superchips in the context of advanced packaging technologies.
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