Nano enabled 3D integration of on-chip ESD protection for ICs

Abstract

This paper reviews recent advances in 3D on-chip electrostatic discharge (ESD) protection design for integrated circuits (IC). Traditional ESD protection relies on PN-junction-based structures, which have inherent disadvantages including fixed ESD triggering and parasitic effects. New ESD protection mechanisms and structures, including nano crystal dots and nano crossbar concepts, provide alternative non-traditional ESD protection solutions enabling post-Si field programmable and above-IC ESD circuit designs. The new ESD protection concepts represent a paradigm change in ESD protection designs and are potential solutions to next-generation nano circuits and systems.