Electrostatic Discharge Protection Research Articles

Highly flexible porous indium-tin-oxide coating with enhanced atomic oxygen and electrostatic discharge resistance

Polyimides (PI) are commonly used in spacecraft in low Earth orbit (LEO) due to their flexibility. However, they are susceptible to erosion caused by atomic oxygen (AO) and electrostatic discharge (ESD) induced by plasma in the harsh LEO environment. Indium-tin-oxide (ITO), owing to its excellent electrostatic and AO resistance, has emerged as the most promising inorganic protective coating for PI in LEO applications. But the inherent rigidity of ITO and the high-temperature annealing process commonly required for synthesis make it challenging to employ ITO as flexible polymer substrates. In this work, we have synthesized the porous ITO layer with a low-temperature (≤150 °C) method and combined it with layer double hydroxides (LDHs) to enhance the flexibility, AO resistance, and ESD protection of the coating. The porous ITO in combination with LDHs layers effectively improve the flexibility (after 20,000 bending cycles without failure problem), AO resistance (erosion yield down to -0.102 × 10−26 cm3/atom under an exposure dose of 5.22 × 1021 atoms/cm2) and ESD resistance properties (sheet resistance around 202 kΩ/sq). The synthesis method proposed avoids the high-temperature annealing and the residual stress effect on the coating's flexibility. This work provides an efficient approach to realizing flexible and protective coating on polymers for long-lasting spacecraft electronic devices in low Earth orbit.

Ferroelectric Domain Wall Delayer and Low-Dropout Regulator.

A switching-type power converter providing an accurate and stable switching output voltage against line/load variations and power supply ripple is mostly complicated in system-on-chip power management integrated circuits (PMICs) within a limited occupation area. Here we fabricated domain wall (DW) nanodevices using an X-cut LiNbO3 thin film on silicon. The domain switching event occurs after a delay time predicted by Merz's law under the applied voltage. But the output current is irrespective of the applied voltage and can be adjusted by conducting wall width as well as input resistance in the circuit. The regulating currents appear repetitively across the volatile interfacial domains between the nanodevice and electrode under intermittently applied voltages. A wall-current-limited domain switching model is developed to explain the phenomenon. The multifunctional DW nanodevices with smaller occupation areas can serve as compact low-dropout regulators in PMICs, time-domain delayers in energy-efficient neural network systems, and on-chip electrostatic discharge protection besides nonvolatile memories and selectors.

Characteristic parameter model and circuit‐level simulation of gate‐controlled dual direction SCR for on‐chip ESD protection

SummaryDual‐directional SCR (DDSCR) with bidirectional discharge paths and high robustness is widely employed for electrostatic discharge (ESD) protection in integrated circuits. However, the design and simulation of on‐chip ESD protection circuits for dual‐directional paths remain challenging due to a lack of relevant device models. This paper designs a Gate‐Controlled Dual‐Direction SCR (GDDSCR) for providing electrostatic discharge (ESD) protection in industry‐level temperature sensors. Furthermore, a new behavioral model is developed based on the GDDSCR for simulating ESD protection circuits along both forward and reverse paths. Experimental results demonstrate that the GDDSCR behavioral model accurately reproduces the IV characteristics observed in bidirectional transmission line pulse (TLP) tests. In addition, the equivalent circuit based on human body model (HBM) is used for transient simulation, and the accuracy of the model is verified by relevant HBM experiments. The proposed model allows the direct extraction of parameters such as trigger voltage (Vt1), holding voltage (Vh), and on‐state resistance (Ron) through TLP testing, facilitating easy application to other types of DDSCR devices.

Wafer-Scale Carbon Nanotubes Diodes Based on Dielectric-Induced Electrostatic Doping.

Diodes based on p-n junctions are fundamental building blocks for numerous circuits, including rectifiers, photovoltaic cells, light-emitting diodes (LEDs), and photodetectors. However, conventional doping techniques to form p- or n-type semiconductors introduce impurities that lead to Coulomb scattering. When it comes to low-dimensional materials, controllable and stable doping is challenging due to the feature of atomic thickness. Here, by selectively depositing dielectric layers of Y2O3 and AlN, direct formation of wafer-scale carbon-nanotube (CNT) diodes are demonstrated with high yield and spatial controllability. It is found that the oxygen interstitials in Y2O3, and the oxygen vacancy together with Al-Al bond in AlN/Y2O3 electrostatically modulate the intrinsic CNTs channel, which leads to p- and n-type conductance, respectively. These CNTs diodes exhibit a high rectification ratio (>104) and gate-tunable rectification behavior. Based on these results, we demonstrate the applicability of the diodes in electrostatic discharge (ESD) protection and photodetection.

Organosilicon elastomers of MWCNTs and nano-sized metals for heating purposes

Silicone elastomers are continuously gaining importance in a variety of industrial applications, including strain gauges, electrical heaters, electromagnetic interference, and electrostatic discharge protection coatings. But these materials have certain drawbacks such as high cost, poor resistance to solvents, low tear strength, limited high-temperature resistance, difficulty in bonding and limited abrasion resistance. Therefore, unique nanocomposites of organosilicon elastomers with metals have been prepared using MWCNTs. The prepared nanocomposites demonstrated nano-diameter structures (15–60 nm) with micron-sized fibrous structures (12–60 μm). Aluminum elongated inclusions (60 µm in size) and bronze spherical inclusions (12–30 µm) were observed in the nanocomposites. The composites containing MWCNTs, Co-Mo/Al2O3-MgO catalyst and bronze (3 wt. %) had the maximum thermal and electrical conductivity. The prepared nanocomposites were used to make the heaters. The heating of the heaters was carried out by applying a voltage of 12–24 V. The Highest temperature achieved was more than 50 °C in all the heaters. By supplying 12–24 V electricity to the heaters in the ventilation and heat recirculation system, the interior of a minibus or living space can be heated. The developed electric heater has another important economic application in temperature-controlled materials.

Characterization of ESD-induced electromigration on CMOS metallization in on-chip ESD protection circuit

Electrostatic discharge (ESD) and electromigration are critical issues that significantly impact the reliability of ICs. While both of these phenomena have been studied independently, the combination of the two, ESD-induced electromigration, has received less attention, potentially compromising IC reliability. This work analyzes various types of metal with different lengths, widths, and angles commonly used in ESD protection circuits in the CMOS process. The objective is to observe their behavior under continuous ESD zapping. The ESD-induced electromigration of metallization in the CMOS process has been analyzed, and metal sensitivity to system-level ESD events has also been identified. It is also analyzed from the perspective of energy that the ESD energy that metal can withstand will decrease as the ESD voltage increases, which will be even more detrimental to the ESD reliability of ICs. The findings from this study aim to provide valuable insights for designing metal lines in ICs to enhance ESD protection.

A novel low trigger voltage low leakage SCR for low-voltage ESD protection

Reducing trigger voltage has always been a research hotspot in low-voltage electrostatic discharge (ESD) protection applications for integrated circuit. Thus, a novel low trigger voltage low leakage silicon-controlled rectifier (LTVLLSCR) for low-voltage ESD protection has been proposed. The proposed device uses a PMOS connected with the SCR to reduce the trigger voltage and the PMOS gate can be applied with the supply voltage to further reduce the trigger voltage and the leakage current. The operating principle and the physical mechanism of the proposed device were discussed by the Human Body Model simulation. The ESD characteristics of the proposed device were verified in 55 nm CMOS process. The experimental results demonstrate that the trigger voltage of the proposed device can reach a minimum of 2.86 V with an external bias, and the leakage current at 25 °C is about 1 nA which can be reduced by 13% with an external bias. With lower trigger voltage, lower leakage, smaller ESD design window and good ESD robustness, the LTVLLSCR is very suitable for 1 V low voltage applications.

Dual-directional SCR device with dual-gate controlled mechanism for ESD protection in photoelectric chip

The dual-directional silicon-controlled rectifier (DDSCR) is an electrostatic discharge (ESD) protection device. It can provide positive and negative ESD surge paths and has excellent robustness. However, industry-level sensors operating in strong electromagnetic interference environments impose higher reliability requirements on photoelectric chips. This paper proposed a novel DDSCR with a dual-gate controlled mechanism. By incorporating the gate diode triggering and the gate field modulation mechanism into the traditional DDSCR, and further utilizing additional parasitic bipolar junction transistors (BJTs) for diversion, the proposed device exhibits significantly improved ESD characteristics. Measurement results indicate that, compared to DDSCR, the proposed device exhibits a 27.5% reduction in trigger voltage (Vt1 ), a 96.1% improvement in holding voltage (Vh ), and achieves an equivalent human body model protection level of 11.45 kV, demonstrating exceptional design area efficiency. The experimental findings validate the effectiveness of the proposed device in 5 V photoelectric chip applications.

High Voltages in Sliding Water Drops.

Water drops on insulating hydrophobic substrates can generate electric potentials of kilovolts upon sliding for a few centimeters. We show that the drop saturation voltage corresponds to an amplified value of the solid-liquid surface potential at the substrate. The amplification is given by the substrate geometry, the drop and substrate dielectric properties, and the Debye length within the liquid. Next to enabling an easy and low-cost way to measure surface- and zeta- potentials, the high drop voltages have implications for energy harvesting, droplet microfluidics, and electrostatic discharge protection.

A Multichannel Electrochemical Sensor Interface IC for Bioreactor Monitoring.

This research article introduces a novel integrated circuit (IC) designed for bioreactor applications catering to multichannel electrochemical sensing. The proposed IC comprises 2x potentiometric, 2x potentiostat, 2x ISFET channels and 1x temperature channel. The potentiostat channel utilizes a current conveyor-based architecture with a programmable mirroring ratio, enabling an extensive measurement range of 114 dB. The potentiometric channel incorporates a customized electrostatic discharge (ESD) protection circuit to achieve ultra-low input leakage in the picoampere range, while the ISFET channel employs a constant-voltage, constant-current topology for accurate pH measurement. Combined with the die temperature sensor, this IC is well-suited for monitoring bioreactions in real-time. Additionally, all channels can be time-multiplexed to a reconfigurable analog backend, facilitating the conversion of input signals into digital codes. The prototype of the IC is fabricated using 0.18 μm standard CMOS technology, and each channel is experimentally characterized. The interface IC demonstrates a peak power consumption of 22 μW.

Preparation of antistatic and biodegradable packaging of PLA/PHBV blend‐based glassy carbon and graphene nanoplatelets composites

AbstractGlassy carbon (GC) and graphene nanoplatelets (GNP) were used as fillers for the preparation of antistatic and biodegradable composites based on poly (lactic acid)/poly(3‐hydroxybutyrate‐co‐3‐hydroxyvalerate) (PLA/PHBV) blend. In this work, PLA/PHBV (80/20) blends with the addition of different GC contents (0.1, 0.3, and 0.5 wt%) were prepared by melt mixing using a twin‐screw extruder, and specimens were injection molded. Furthermore, hybrid composites were prepared with the addition of 5 wt% of GNP and different GC contents (0.1, 0.3, and 0.5 wt%) using the same processing. The effect of the addition of GC and GNP on the mechanical, electrical, and electromagnetic properties and its effect on the biodegradability of the PLA/PHVB blend was evaluated. The simultaneous addition of GC (0.3 and 0.5 wt%) and GNP (5 wt%) significantly increases the elastic modulus and decreases the electrical resistivity, becoming suitable for electrostatic discharge protection packaging applications. The hybrid composite GC0.5/GNP5 reached a maximum value of total attenuation (4.5 dB), which corresponds to 60% EMI shielding. The degree of crystallinity affects biodegradability more than the type or presence of carbon material. After 110 days of anaerobic biodegradation, the hybrid composite exhibited 10% biodegradability due to the high degree of crystallinity that hinders the biodegradability process. The hybrid composites with the addition of GC and GNP are very promising for use in antistatic packaging.

On-chip ESD Protection Design Methodologies by CAD Simulation

Electrostatic discharge (ESD) can cause malfunction or failure of integrated circuits (ICs) . On-chip ESD protection design is a major IC design-for-reliability (DfR) challenge, particularly for complex chips made in advanced technology nodes. Traditional trial-and-error approaches become unacceptable to practical ESD protection designs for advanced ICs. Full-chip ESD protection circuit design optimization, prediction, and verification become essential to advanced chip designs, which highly depends on CAD algorithm and simulation that has been a constant research topic for decades. This paper reviews recent advances in CAD-enabled on-chip ESD protection circuit simulation design technologies and ESD-IC co-design methodologies. Key challenges of ESD CAD design practices are outlined. Practical ESD protection simulation design examples are discussed.

Research on Optimal Design of Chip ESD Protection Circuit Based on CMOS Technology

A high frequency circuit based on ESD protection and a new type of power grounding clamp circuit are designed. The oblique edge interfinger diode is used to achieve the optimal design of layout and performance. The design of electrostatic discharge protection circuit and flowsheet were completed in Jazz0.18-micron silicon germanium BiCMOS process. The protection voltage of electrostatic discharge is 3000 V. Higher electrostatic protection level can be obtained by changing the bifurcation index of diode. Improved protection of up to 4500 volts can be achieved. Through the test of the chip, it is proved that the chip fully meets the design requirements and can realize various types of digital circuits.

Design and verification of a hybrid electrostatic discharge model for Gate-Controlled silicon controlled rectifier

The DC breakdown characteristic of electrostatic discharge (ESD) protection device, which is an important indicator of its transparency and circuit compatibility, has received widespread attention. Currently, methods such as Verilog-A hardware description language, circuit-level SPICE simulation, and process-level device modeling cannot simultaneously achieve high accuracy, good convergence, and fast simulation speed. Therefore, in this paper, a hybrid ESD model based on Technology Computer Aided Design (TCAD) device-level simulation, Monte Carlo numerical modeling and Verilog-A behavioral modeling is proposed to characterize the ESD characteristics of gate-controlled silicon-controlled rectifier (GCSCR). A device-level model of GCSCR was established using TCAD, and the working mechanism was simulated. By extracting the electric field from TCAD and using the Monte Carlo modeling method, the DC characteristic of GCSCR was accurately characterized. In addition, the snapback characteristic of the device was successfully simulated by Verilog-A. The effectiveness of the above approaches was further verified based on the 0.18 μm standard BCD (Bipolar-CMOS-DMOS) process. Comparison results indicate that the hybrid model exhibits high simulation accuracy, good convergence and good universality and scalability, providing a simple and effective modeling solution for ESD devices of different structures and sizes.1This work is supported by the National Natural Science Foundation of China (Grant No. 62174052, 61827812), Hunan Science and Technology Department Huxiang High-level Talent Gathering Project (Grant No. 2019RS1037) and Innovation Project of Science and Technology Department of Hunan Province (Grant No. 2020GK2018).

High Area Efficiency Bidirectional Silicon-Controlled Rectifier for Low-Voltage Electrostatic Discharge Protection

Continuously scaling down and decreasing operation voltages of ICs, from the 5 V TTL-compatible voltage to 3.3 V, then 1.2 V, and now 0.8 V for low-power ICs, results in more stringent electrostatic discharge protection design requirements, such as a narrow ESD design window, low operation voltage, and high ESD robustness. Based on traditional diode string and diode-triggered silicon-controlled rectifiers, an enhanced diode-triggered silicon-controlled rectifier is proposed to meet the requirements of low-voltage integrated circuits as bidirectional electrostatic discharge protection. The new device employs an additional PMOS and NMOS in the N-well and P-well, respectively, to offer additional current paths along the surface to significantly enhance its robustness. TCAD simulation shows that the device is triggered by both the diode strings and embedded MOS, making the device turn on faster and the current distribution more uniform during the ON state owing to the additional surface current paths. The proposed new device has excellent dual-directional ESD protection performance with a figure of merit of 4.01 mA/um2, which is about a 71% improvement compared with the conventional diode-triggered silicon-controlled rectifier. It also has higher area efficiency, lower trigger voltage, lower current leakage, and a faster turn-on speed. The proposed enhanced diode-triggered silicon-controlled rectifier is an attractive ESD protection solution for ultra-low-voltage ICs.

ESD Research of SCR Devices under Harsh Environments.

In prior technology, system-level electrostatic discharge (ESD) tests under environment change conditions mainly focused on testing the effect of a high-temperature environment. i.e., the effect on internal circuits of heat generated outside. However, few studies have explored the effect of ambient relative humidity changes on integrated circuits (ICs). Therefore, this study will analyze the performance of various ESD protection components under high ambient temperature and high ambient relative humidity. The ESD protection devices are tested for the ESD robustness of the silicon-controlled rectifiers (SCR) under a harsh environment and the measurement results are discussed and verified in the CMOS process.

Steering triboelectric and mechanical properties of polymer fibers with carbon black

The development of wearable electronics has spurred an increased interest in self-powered systems and triboelectric nanogenerators (TENGs). To enhance the output performance of TENGs, researchers have dedicated significant efforts toward finding effective ways to increase triboelectric and mechanical performance. This study examined how conductive carbon black (CB) affects the mechanical and triboelectric properties of electrospun fibers made of polyurethane (PU), polystyrene (PS), and polycarbonate (PC). The addition of CB affected their mechanical properties, including increased tensile strength and decreased elongation at break. Importantly, triboelectric testing revealed that incorporating CB decreased the triboelectric output of PU and PS by over 90%, while it increased the output of PC by 260%. These findings indicate that CB's effects on triboelectric properties depend on the material and its content, underscoring the importance of selecting CB content carefully for optimal mechanical and triboelectric performance in electrospun fibers and composites. This research validates the development of advanced composite materials for electrostatic discharge protection and energy harvesting applications.

A novel robust SCR with high holding voltage for on-chip ESD protection of industry-level bus

In an industry-level bus, strong electrostatic interference seriously threatens the reliability of chips. However, the holding voltage (Vh) and robustness of traditional silicon-controlled rectifier (SCR) cannot meet the electrostatic discharge (ESD) window of industry-level applications. To better cope with extreme environments, this paper proposes a novel SCR with high robustness and latch-up immunity for on-chip ESD protection of the industry-level RS485 bus. By incorporating a surface current diverting path into the traditional SCR, the ESD characteristics of the proposed device are significantly improved. Through two-dimensional device simulation, the ESD characteristics of traditional SCR, proposed P-Well Floating SCR (PFSCR) and proposed P-Well Grounded SCR (PGSCR) are compared, with a focus on exploring the role of surface discharge path. Three types of SCR are realized based on the 0.18 μm BCD process. The transmission line pulse (TLP) test results show that PGSCR (13.64 V) has a higher Vh and higher robustness than traditional SCR (2.13 V) and PFSCR (4.39 V). In addition, the trigger voltage (Vt1:22.9 V) and failure current (It2:18.49A) of the PGSCR fully meet the ESD window of the target chip.

Temperature dependence of ESD effects on 28 nm FD‐SOI MOSFETs

AbstractThe failure mechanisms caused by electrostatic discharge (ESD) effects at ambient temperatures ranging from −75 to 125°C are investigated by Silvaco TCAD simulator. The devices are NMOS transistors fabricated with 28 nm fully depleted silicon‐on‐insulator (FDSOI) technology. Results indicate that with an increase in temperature, the first breakdown voltage of the device decreased by 27.32%, while the holding voltage decreased by approximately 8.49%. The total current density, lattice temperature, potential, and so forth were extracted for a detailed insight into the failure process. These findings provide valuable references for the design and development of ESD protection devices applied at different temperature ranges.

Design of Destruction Protection and Sustainability Low-Dropout Regulator Using an Electrostatic Discharge Protection Circuit

In terms of sustainable power semiconductors, the embedding of an electrostatic discharge (ESD) protection circuit in an integrated circuit (IC) is an important aspect. In order for the semiconductor circuit to operate continuously or stably, a sufficient protection circuit against external surges must be configured. The purpose of this thesis is not only to effectively operate the low-dropout (LDO) regulator according to the load current, but to also secure high reliability against ESD situations by embedding an ESD protection circuit at the IC level. Moreover, the existence and nonexistence of an ESD protection circuit at the IC level is directly related to reliability. The proposed LDO regulator has high reliability against ESD situations using an embedded silicon controlled rectifier (SCR)-based ESD protection circuit in the I/O clamp and power clamp. The results revealed that the LDO regulator can not only effectively control the output voltage according to the load current, but it can also stably maintain the output voltage against the ESD surge. Moreover, the proposed LDO regulator with an embedded ESD protection circuit implemented in a 0.13 μm BCD process maintained an undershoot voltage of 21 mV and overshoot voltage of 19 mV for a load current of 300 mA.