Electrostatic Discharge Protection Devices Research Articles

Modeling of enclosed-gate layout transistors as ESD protection device based on conformal mapping method

This paper proposes a novel technique for modeling the electrostatic discharge (ESD) characteristic of the enclosed-gate layout transistors (ELTs). The model consists of an ELT, a parasitic bipolar transistor, and a substrate resistor. The ELT is decomposed into edge and corner transistors by solving the electrostatic field problem through the conformal mapping method, and these transistors are separately modeled by BSIM (Berkeley Short-channel IGFET Model). Fast simulation speed and easy implementation is obtained as the model can be incorporated into standard SPICE simulation. The model parameters are extracted from the critical point of the snapback curve, and simulation results are presented and compared to experimental data for verification.

A Design of BJT-based ESD Protection Device combining SCR for High Voltage Power Clamps

This paper presents a novel bipolar junction transistor (BJT) based electrostatic discharge (ESD) protection device. This protection device was designed for 20V power clamps and fabricated by a process with Bipolar-CMOS-DMOS (BCD) 0.18μm. The current-voltage characteristics of this protection device was verified by the transmission line pulse (TLP) system and the DC BV characteristic was verified by using a semiconductor parameter analyzer. From the experimental results, the proposed device has a trigger voltage of 29.1V, holding voltage of 22.4V and low on-resistance of approximately 1.6;. In addition, the test of ESD robustness showed that the ESD successfully passed through human body model (HBM) 8kV. In this paper, the operational mechanism of this protection device was investigated by structural analysis of the proposed device. In addition, the proposed device were obtained as stack structures and verified.

A novel DTSCR with a variation lateral base doping structure to improve turn-on speed for ESD protection

The turn-on speed of electrostatic discharge (ESD) protection devices is very important for the protection of the ultrathin gate oxide. A double trigger silicon controlled rectifier device (DTSCR) can be used effectively for ESD protection because it can turn on relatively quickly. The turn-on process of the DTSCR is first studied, and a formula for calculating the turn-on time of the DTSCR is derived. It is found that the turn-on time of the DTSCR is determined mainly by the base transit time of the parasitic p–n–p and n–p–n transistors. Using the variation lateral base doping (VLBD) structure can reduce the base transit time, and a novel DTSCR device with a VLBD structure (VLBD_DTSCR) is proposed for ESD protection applications. The static-state and turn-on characteristics of the VLBD_DTSCR device are simulated. The simulation results show that the VLBD structure can introduce a built-in electric field in the base region of the parasitic n–p–n and p–n–p bipolar transistors to accelerate the transport of free-carriers through the base region. In the same process and layout area, the turn-on time of the VLBD_DTSCR device is at least 27% less than that of the DTSCR device with the traditional uniform base doping under the same value of the trigger current.

ESD Protection Device With Dual-Polarity Conduction and High Blocking Voltage Realized in CMOS Process

Electrostatic discharge (ESD) protection devices fabricated in a low-voltage CMOS process for communication interface applications typically provide relatively small blocking voltage, thus limiting the interface operating voltage range for which the ESD device can be used. This letter introduces a CMOS-based silicon controlled rectifier with a large blocking voltage beyond ±20 V and a high trigger current. Such a high blocking voltage is achieved by selectively defining native-buffer regions in critical blocking junctions of the device. Experimental characterization of the ESD robustness and standing operation are presented to validate the new device for low capacitance, high-voltage-tolerant communication interface ESD protection applications.

An investigation on capacitance-trigger ESD protection devices for high voltage integrated circuits

A novel cascaded complementary dual-directional silicon controlled rectifier (CCDSCR) structure has been proposed and implemented in a 0.5μm 20V Bipolar/CMOS/DMOS process as an ESD (electrostatic discharge) protection device. The ESD characteristics of the capacitance-trigger CCDSCR has been investigated by transmission line pulse (TLP) testing. Compared with the substrate-trigger insulated gate bipolar transistor with the enhanced substrate parasitic capacitance, the gate-driven trigger insulated gate bipolar transistor with the gate coupling capacitance and the normal dual-directional silicon controlled rectifier, the CCDSCR has the highest holding voltage of about 25.4V and the best current conduction uniformity. In addition, it has the best figure of merit (FOM) with the value of about 0.64mA/μm2. The good current conduction uniformity in CCDSCR due to the enhanced substrate parasitic capacitance-trigger effect is finally confirmed by Sentaurus simulations.

Research on the Behavior of Transient Voltage Suppressor as ESD Protection Device

Electrostatic discharge (ESD) is a major failure mechanism for electronic equipment, and transient voltage suppressor (TVS) is the chief means by which the susceptibility to ESD of equipment can decrease. To study the suppressing behavior of TVS to ESD, a testing system was developed, consisting of the ESD generator, the coaxial-test clamp, the 30dB pulse attenuators, current/voltage sensor,and the oscillograph, etc. Using the testing system, the voltage-current behavior of a TVS as a protection device against ESD is described. It is shown that the pulse clamping voltage and the current peak of the TVS increase with the growth of the injected test voltage, and they are linear with the testing voltage. Through comparing and analyzing, it could be concluded that, for the ESD, using the clamping voltage decided by the same response time to estimate the protection performance of TVS is reasonable.

A Contactless Sensing Analysis of a CUP Wafer

The detected structures in a CUP wafer by sensing (leakage) analysis are presented in this paper. The pad structures are designed by the ADS2009 & TSMC 0.18um CMOS processes design rules, and use some electrostatic discharge (ESD) protection devices and circuits under these pads. Furthermore, the signal will be passed through these ESD devices or circuits on the top-metal pad as a sinusoidal, square, or ESD pulse waveform being injected. It is found that during an ESD occurred situation, a strong signal coupling can be sensed by the ESD protection circuits.

Electro-Static Discharge Protection Design for V-Band Low-Noise Amplifier Using Radio Frequency Junction Varactor

The RF junction varactors are employed as electro-static discharge (ESD) protection devices and co-designed with 60 GHz low-noise amplifier (LNA) fabricated in a 65-nm CMOS technology. The junction varactor acts as an ESD diode to bypass ESD current during ESD zapping, and also utilized as a capacitor to be a part of input matching network of the LNA in normal RF operation. By transmission line pulse (TLP) measurement, the ESD protection capabilities of RF junction varactors are characterized with different device parameters. The experimental results demonstrate excellent second breakdown currents (It2) and high ratios of the ESD levels to parasitic capacitances (VESD/CESD). With ESD/matching co-design methodology, the ESD-protected LNA demonstrates a second breakdown current It2 of 1.4 A, corresponding to a 2-kV human-body-model (HBM) ESD protection level with a noise figure (NF) of 6.6 dB and a peak gain of 16.5 dB at 60 GHz under a power consumption of only 28 mW.

A compact model of substrate resistance for deep sub-micron gate grounded NMOS electrostatic discharge protection device

The current controlled voltage source model of substrate parasitic resistance of deep sub-micron electrostatic discharge protection device is optimized by considering the effect of conductance modulation. A compact macro-model of substrate resistance is presented according to the characteristics of lightly doped bulk substrate and heavily doped substrate with a lightly doped epitaxial layer, which is scalable with the layout dimension. The experimental model parameters of devices with various spaces between source and substrate diffusion can be extracted by device simulation. The breakdown behavior of gate grounded negative-channel metal oxide semiconductor shows the effectiveness of this method. In the meantime, the simulation time-consuming of the compact model is only 7% that of the device simulation software.

Bidirectional Diode-Triggered Silicon-Controlled Rectifiers for Low-Voltage ESD Protection

A new bidirectional electrostatic discharge (ESD) protection device is reported in this letter. It consists of a bidirectional silicon-controlled rectifier and diode strings. Such a structure can offer an effective ESD protection solution for low-voltage integrated circuits due to its small design window, small footprint, and high ESD robustness.

Effect of Elevated Ambient Temperature on Thermal Breakdown Behavior in BCD ESD Protection Devices Subjected to Long Electrical Overstress Pulses

We investigate the effect of elevated ambient temperature on thermal breakdown (TB) modes in linear-geometry electrostatic discharge (ESD) protection n-p-n transistors of smart power technology subjected to 0.5-1- μs-long ESD pulses. The current transport in these devices has a form of traveling current filaments (CFs) where TB at room temperature occurs at one of the device ends. An increase in ambient temperature gives rise additionally to another failure mode, inside the device. For the failure mode at the device end, the increase of ambient temperature in the range up to 100°C causes shortening of the averaged time to TB 〈 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TB</sub> 〉 by a duration that the CF needs for one round trip over the device width. At ambient temperatures up to 180°C, the TB may occur even at initial triggering CF position inside the device, before the CF starts to move. The ambient temperature at which the transition between CF modes with different 〈 <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">t</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">TB</sub> 〉 occurs is investigated as a function of stress current. Furthermore, inspecting the failure current of devices with different widths shows that there is an equivalence between the effect of increased ambient temperature and the effect of the preheating at the device end by a previous CF passage. The experiments are supported by 3-D thermal simulation of temperature in moving and standing CFs.

An optimized UWB correlator design with the consideration of the impacts from the ESD protection devices

Electrostatic discharge (ESD) failure has become an emerging challenge for radio frequency (RF) integrated circuits (ICs), which requires high ESD-protection for circuit applications in harsh environment. This paper discusses the design and optimization of an ultra-wideband (UWB) correlator circuit using ESDaware simulation design technique. Mixed-mode ESD simulation-design method and RF ESD characterization technique are presented for accurate ESD device design and ESD-induced parasitic effects extraction. The impact of ESD induced parasitic is carefully considered in the whole correlator design simulation by using a direct S-parameter insertion technique. The design is based on a commercial 0.18 μm RFCMOS technology.

Modal filter as a device for electrostatic discharge protection of onboard computers and control units of space vehicles

The urgency of the development of new devices for electrostatic discharge (ESD) protection of onboard computers and control units of space vehicles is demonstrated. Physical and technical principles of integral protection based on modal filtration are briefly described. For the first time, the specific features of the ESD excitation on the modal filter (MF) are considered. Preliminary simulation results of conductive excitation current source according to the IEC 61000-4-2 standard on the MF in the form of a flexible printed cable are presented. The existence of an optimal MF length and inexpediency of its further increase, the attenuation by 30% for optimal MF length, and the importance of modal filtration for better ESD protection of onboard computers and control units of space vehicles are demonstrated.

Investigation of the polysilicon p-i-n diode and diode string as a process compatible and portable ESD protection device

The polysilicon p-i-n diode displays noticeable process compatibility and portability in advanced technologies as an electrostatic-discharge (ESD) protection device. This paper presents the reverse breakdown, current leakage and capacitance characteristics of fabricated polysilicon p-i-n diodes. To evaluate the ESD robustness, the forward and reverse TLP I–V characteristics were measured. The polysilicon p-i-n diode string was also investigated to further reduce capacitance and fulfill the requirements of tunable cut-in or reverse breakdown voltage. Finally, to explain the effects of the device parameters, we analyze and discuss the inherent properties of polysilicon p-i-n diodes.

Two-stage trigger silicon-controller rectifier (SCR) for radio-frequency (RF) input and output protections in nanometer technologies

In this paper, a two-stage trigger (TST) scheme is proposed to implement a low-capacitance and zero-ohm input resistance electrostatic-discharge (ESD) protection device for nanometer technology applications. Besides the main trigger device diode string, the output transistor can also be used as the trigger device. The dimension of the main trigger device can be reduced for minimizing its capacitance with the additional trigger device. Moreover, the output transistor can be as the driving device without any series resistor. This is because the diode string can help to prevent integrated circuits (ICs) from ESD damage before the primary ESD protection device turns on.

Electrostatic discharge (ESD) protection of N-type silicon controlled rectifier with P-type MOSFET pass structure for high voltage operating I/O application

An electrostatic discharge (ESD) protection device, so called, N-type silicon controlled rectifier with P-type MOSFET pass structure (NSCR_PPS), was analyzed for high voltage I/O applications. A conventional NSCR_PPS device shows typical SCR-like characteristics with extremely low snapback holding voltage, which may cause latchup problem during normal operation. However, our modified NSCR_PPS device with proper junction/channel engineering such as counter pocket source (CPS) structure demonstrates highly latchup immune current–voltage characteristics. Methodology for the junction/channel engineering and the related operation mechanisms are discussed in terms of thermal effects incorporated device simulation results.

The Investigation of Electrothermal Characteristics of High-Voltage Lateral IGBT for ESD Protection

In this paper, the detailed characterizations of the lateral insulated-gate bipolar transistor (LIGBT) for the electro- static discharge (ESD) protection of power ICs are presented. Compared with the conventional lateral DMOS with the same structure except for the anode doping type, the LIGBT shows lower triggering voltage, faster voltage-clamping speed, and much higher ESD robustness. Experimental results demonstrate that the LIGBT with runway layout achieves excellent thermal breakdown current of more than 10 A with 250-μm device width. The high ESD performance enables the LIGBT to be used as a promising ESD protection device in the power ICs.

Analysis of reliability and optimization of ESD protection devices supported by modeling and simulation

An analysis of electrostatic discharge (ESD) protection structures supported by advanced 2-D mixed mode electro-thermal device and circuit simulation with calibrated electro-physical models to increase the reliability of protected IC’s is presented. The critical temperature as a criterion of device destruction is defined and experimentally verified. Numerical simulation and visualization of the internal electro-physical properties of the analyzed structures during a very short ESD pulse considerably improved the understanding of their physical behavior and contributes to a proper design and optimization of doping and geometry of the analyzed ESD protection devices. The analyzed devices are designed as protection against Human Body Model (HBM) and International Electromechanical Commission model (IEC) 61000-4-2 with very high robustness. The obtained results are shown on two examples. Modification of the device layout by splitting the cathode contact of the ESD diode into two parts allowing area reduction with improved electrical characteristics is the subject of the first example. The influence of doping fluctuations on the device robustness is presented in the second example. Different triggering and failure mechanisms of the diode and transistor structure during HBM and IEC pulse are presented.

Semiself-Protection Scheme for Gigahertz High-Frequency Output ESD Protection

In this paper, a semiself-protection scheme is proposed and developed for gigahertz output electrostatic-discharge (ESD) protection. The output transistor acts as a trigger device to trigger the ESD protection device, and then, it is turned off when the ESD protection device turns on. Thus, the capacitance of a gigahertz high-frequency output pad can be minimized because this scheme is without any additional trigger device or any passive component.

Complete Time-Domain Diode Modeling: Application to Off-Chip and On-Chip Protection Devices

Protection elements are commonly used in electronic systems: digital integrated circuits (ICs) include built-in electrostatic discharge protection devices, and sensitive lines or printed circuit boards traces are often protected using discrete elements, such as clamping or Zener diodes. In order to know if a perturbation is able to disturb or damage ICs, the actual level of signal entering the digital core of the components must be accurately determined, taking into account all the effects of the protection devices. Thus, assessing the perturbation signal at IC core level requires accurate models of the protection elements, even in the case they are inactive. Therefore, this paper focuses on the experimental and theoretical evaluation of the protective behaviors and parasitic effects of these elements. Some limitations of the standard SPICE diode and IBIS models are discussed, and a modeling methodology is presented. Based on a time-domain characterization method associated with a parameter-extraction procedure for enhanced SPICE diode models, the methodology is applied to both discrete and on-chip protection devices and has a good agreement with measurement.