Complete Time-Domain Diode Modeling: Application to Off-Chip and On-Chip Protection Devices

Abstract

Protection elements are commonly used in electronic systems: digital integrated circuits (ICs) include built-in electrostatic discharge protection devices, and sensitive lines or printed circuit boards traces are often protected using discrete elements, such as clamping or Zener diodes. In order to know if a perturbation is able to disturb or damage ICs, the actual level of signal entering the digital core of the components must be accurately determined, taking into account all the effects of the protection devices. Thus, assessing the perturbation signal at IC core level requires accurate models of the protection elements, even in the case they are inactive. Therefore, this paper focuses on the experimental and theoretical evaluation of the protective behaviors and parasitic effects of these elements. Some limitations of the standard SPICE diode and IBIS models are discussed, and a modeling methodology is presented. Based on a time-domain characterization method associated with a parameter-extraction procedure for enhanced SPICE diode models, the methodology is applied to both discrete and on-chip protection devices and has a good agreement with measurement.