Electrostatic Discharge Failure Research Articles

Study on ESD Protection Circuit by TCAD Simulation and TLP Experiment

The anti-ESD characteristic of the electronic system is paid more and more attention. Moreover, the on-chip electrostatic discharge (ESD) is necessary for integrated circuits to prevent ESD failures. In this paper, the mixed TCAD model of the ESD protection circuit is built and simulated, and the negative transmission line pulse (TLP) injection damage experiment is carried out on the CD4069UBC chip. The circuit model consists of three-dimensional shallow trench isolation (STI) diode TCAD models and a three-dimensional multi-gate Complementary Metal-Oxide-Semiconductor (CMOS) inverter TCAD model. Moreover, the TCAD modeling is based on a 0.25 μm technology node. Through the transient simulation of the electrothermal coupling, the electrical signal of the input and output nodes of the circuit and the distribution of the electrothermal parameters in the device are obtained. Moreover, by analyzing the simulation results, the physical phenomena and the mechanisms of interference and damage mechanism during TLP injection are explained. The location and type of diode damage in the TLP injection simulation results of the circuit model are consistent with the TLP experiment damage results. The proposed ESD protection circuit model and analysis method are beneficial to ESD robustness prediction and ESD soft damage analysis of IC.

Research on ESD failure voltage model of the T-shaped wiring structure in GOA products

In the GOA (Gate on Array) circuits, which are commonly employed in LCD (Liquid Crystal Display) products, the metal wire layers have been found to be sensitive to ESD (Electrostatic Discharge) in production, leading to an increase in the failure rate of GOA products, especially in T-shaped wiring structures. In this paper, we conducted a study on the relationship between the ESD failure voltage and structure parameters of T-shaped wiring structures in GOA products to enhance their reliability. We established an ESD failure voltage model for T-shaped wiring structures based on the relevant electrical breakdown theory. And failure voltage and gap breakdown voltage data are required for accurate model parameters fitting. Hence, ESD tests on the T-shaped wiring structure samples were conducted. In addition, ESD simulation of T-shaped wiring structure using CST software was applied to supply gap voltage data unavailable from tests. Based on the results of the tests and simulation, parameters of the ESD failure voltage model were fitted. And we performed the model modification using verification tests for higher accuracy. The results show that our model errors are below 5 %. Guided by the ESD failure voltage model, a more reliable T-shaped structure can be produced in GOA.

19‐4: Triboelectric Discharging Problems in QD‐OLED Manufacturing and Solutions Using Electromagnetic Analysis

Triboelectric discharging failure is one of the major quality issues of QD‐OLED display, which is the top priority failure item in the QD‐OLED manufacturing process. In order to prevent electrostatic discharge (ESD) failure of the QD‐OLED, triboelectric discharging phenomena of the full panel size should be assessed and proper precautions should be taken before the mask tape‐out. In this paper, ESD failure mechanism during the thin film fabrication process is investigated by using the numerical analysis and verified by experiments. ESD failure criterion of the QD‐OLED devices is characterized by using the spider mask. ESD failure rate of QDOLED displays and the electric field strength of the model are compared to establish the reliable ESD prediction model. For the first time, full panel scale ESD failure evaluation methodology is developed, and the electromagnetic behavior of the accumulated charges in the display panel is explored. Based on the newly developed methodology, ESD robust QD‐OLED panel design is suggested and experimentally verified. Finally, we achieved zero ESD defects during the production process for the QD‐OLED.

Electrostatic discharge failure characteristics of oxide vertical cavity surface emitting lasers

The predecessor of China Optics was China Optics and Applied Optics Digest, which was founded in 1985. At that time, it was the only retrieval journal in the field of optics in China. At the end of 2008, China Optics and Applied Optics Digest was renamed

Non-Pad-Based in Situ In-Operando CDM ESD Protection Using Internally Distributed Network

Charged device model (CDM) electrostatic discharge (ESD) protection is an emerging design challenge to ICs at advanced technology nodes. It was recently reported that the traditional pad-based CDM ESD protection methods are fundamentally faulty, which causes uncertainties in CDM ESD protection designs, testing and failure analysis. Re-thinking of onchip CDM ESD protection becomes imperative for complex ICs implemented in advanced technologies. This paper reports a disruptive CDM ESD protection method utilizing non-pad-based internally-distributed ESD protection network as a robust in situ in-operando CDM ESD protection solution. The proposed internal-distributed CDM ESD protection mesh network can be realized using interposer or through-silicon-via (TSV) ESD protection structures to achieve local 3D CDM ESD protection via heterogeneous integration. The new concept was validated using an internal-CDM-protected oscillator IC implemented in a foundry 45nm silicon-on-insulator (SOI) technology.

TCAD Simulation Study of ESD Behavior of InGaAs/InP Heterojunction Tunnel FETs

For the first time, we investigated the electrostatic discharge (ESD) behavior of an InGaAs/InP heterojunction tunneling field effect transistor (HTFET). The device structure in this study has a high on-state current without extra process steps. Under the positive transmission line pulse (TLP) simulation, the band-to-band tunneling (BTBT) current acts as an important initial current to accelerate the occurrence of impact ionization and the device is turned on quickly. Under the negative transmission line pulse (TLP) simulation, the operating principle of the HTFET is the same as for a poly-bounded diode. The ESD robustness of the device under TLP simulation are evaluated, and the impact factors, with regard to ESD robustness and failure mode, are discussed. Finally, the device behavior under very fast transmission line pulse (VFTLP) simulations with different rise times and pulse widths is also investigated. The results show that this device may be used for the ESD protection of next-generation III–V technology.

Distinct Failure Modes of AlGaN/GaN HEMTs Under ESD Conditions

This article reports the distinct failure mechanisms and insights on device degradation of AlGaN/GaN high electron mobility transistors (HEMTs) under electrostatic discharge (ESD) stress conditions. The role of device surface, MESA isolation, and gate Schottky junction in defining the degradation type is discovered. Premature breakdown at the MESA Schottky junction and dislocation induced failure in the active region and their consequences on ESD robustness are reported. Physical mechanisms responsible for snapback instability in transmission line pulsing (TLP) characteristics are discussed. Change in device failure from soft to hard with pulsewidth is revealed. Finally, the role of contact resistivity, surface diffusion, and channel electric field and its fringing effect at contacts are analyzed in context to ESD failure of AlGaN/GaN HEMTs. Various stages of device degradation during TLP stress are captured on-the-fly using high-resolution (HR) optical microscopy and high-speed Si charge-coupled device (CCD) detector. Postdevice failure, damaged regions are analyzed using transmission electron microscopy and scanning electron microscopy together with in situ energy-dispersive X-ray spectroscopy to probe details of failure mechanisms involved. Finally, based on the learning from this article, design guidelines for an ESD robust HEMT are proposed.

An Enhanced Gate-Grounded NMOSFET for Robust ESD Applications

Gate-grounded n-channel MOSFET (GGNMOS) has been widely used in electrostatic discharge (ESD) protection applications. In this letter, an enhanced GGNMOS, called the EGGNMOS, is proposed and demonstrated. The new device has the same topology as the conventional GGNMOS, except that a few P+ regions are being added to the N+ guard ring (NGR). This novel approach enables the formation of parasitic silicon-controlled rectifiers (SCR’s), thus, resulting in a much higher current handling capability in the EGGNMOS than the GGNMOS under the same silicon footprint. Our experimental results indicate that the proposed EGGNMOS, with an ESD design window suitable for 5V-CMOS technologies, could achieve an ESD failure current density eight time higher that the GGNMOS. Moreover, the transient overshoot characteristic of EGGNMOS is comparable with that of the GGNMOS. Three-dimensional TCAD simulation has also been carried out to verify that the NGR isolation functionality of EGGNMOS is not being comprised.

A High-Speed Si-Based Power Transistor With Bipolar-Assisted Gate Discharging Behavior

This letter presents a novel super junction (SJ) device integrated with an on-chip bipolar junction transistor (BJT) connected between the gate and the source. This parallel path through the BJT to discharge the gate of the SJ device reduces its switch-off time by 26%. It also raises the human-body model electro-static discharge failure threshold from 1.5 to 2.3 kV for the same chip size. In addition, gate voltage oscillation during the switch-off transient is effectively suppressed.

Electro-static discharge protection analysis and design optimization of interlayer Cu interconnection in InGaZnO thin film transistor backplane

The InGaZnO thin film transistor (IGZO TFT) backplane combined with Cu interconnection has nearly an order of magnitude lower in the ability to withstand voltage than that of traditional a-Si TFT backplane on the production line. The breakdown voltage of Mo/Cu interconnection between data line and gate line is only about 60% of that of traditional a-Si TFT backplane. The electrostatic discharge (ESD) breakdown of Mo/Cu:SiN<sub><i>x</i></sub>/SiO<sub>2</sub>:Mo/Cu structure has become an important factor affecting the normal display of IGZO TFT ultra high definition (UHD) panel. We find that the anti-ESD damage ability of IGZO TFT devices needs matching with the anti-ESD damage ability of interlayer Cu interconnection in order to achieve a high-robustness IGZO TFT backplane. The position of ESD damage in IGZO TFT backplane is commonly in the climbing place where the data line crosses the scanning line. In this paper, a Cu diffusion model is proposed to explain the mechanism for the ESD failure of interlayer Cu interconnection. The Cu metal in gate line diffuses into SiN<sub><i>x</i></sub>/SiO<sub>2</sub> gate insulator, and Cu metal at the corner of data line, where the date line crosses the gate line, diffuses into SiO<sub>2</sub> film on the date line. The selection conditions of three kinds of protection architectures for ESD protection circuits around Cu interconnection, i.e. R-type, R-half-type, and Diode-type protection architectures, are proposed. On the basis of process optimization such as Cu metal film forming and Cu metal interface treatment, an ESD protection method for the Cu interconnection periphery of IGZO TFT backplane with high robustness is proposed. For the stable production process of IGZO TFT, combined with the design window of ESD protection circuit, the peripheral ESD protection circuit of Cu interconnect is designed with diode-type protection circuit on the IGZO TFT backplane of large-sized UHD and QUHD panel, which effectively improves the effect of interlayer Cu interconnection of IGZO TFT backplane on ESD damage. Through the production verification, it is proved that the metal diffusion of Cu interconnection on IGZO TFT backplane is the fundamental reason for reducing the anti-ESD damage ability of Mo/Cu:SiN<sub><i>x</i></sub>/SiO<sub>2</sub>:Mo/Cu structure. The rationality of the proposed ESD damage model for interlayer Cu interconnection is verified, which provides a theoretical basis for subsequent IGZO TFT backplane design with high robustness.

Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

There is a risk of InGaZnO thin film transistor (IGZO TFT) failure, especially electro-static discharge (ESD) damage of gate driver on array (GOA) circuits, due to the combination of Cu interconnect, InGaZnO (IGZO) active layer and SiN<i><sub>x</sub></i>/SiO<sub>2</sub> insulating layer used to realize large-scale ultra-high resolution display. It is found that the IGZO TFT damage position caused by ESD occurs between the source/drain metal layer and the gate insulator. The Cu metal of gate electrode diffuses into the gate insulator of SiN<sub><i>x</i></sub>/SiO<sub>2</sub>. The closer to the ESD damage area the IGZO TFT is, the more serious the negative bias of its threshold voltage (<i>V</i><sub>th</sub>) is until the device is fully turned on. The IGZO TFT with a large channel width-to-length ratio(<i>W</i>/<i>L</i>) in GOA circuit results in a serious negative bias of threshold voltage. In this paper, the ESD failure problem of GOA circuit in the IGZO TFT backplane is systematically analyzed by combining the ESD device level analysis with the system level analysis, which combines IGZO TFT device technology, difference in metal density between GOA region and active area on backplane, non-uniform thickness distribution of gate metal layer and gate insulator and so on. In the analysis of ESD device level, we propose that the diffusion of Cu metal from gate electrode into SiN<sub><i>x</i></sub>/SiO<sub>2</sub> leads to the decrease of effective gate insulator layer, and that the built-in space charge effect leads to the decrease of the anti-ESD damage ability of IGZO TFT. In the analysis of ESD system level, we propose that the density of metal layers in GOA region is 4.5 times higher than that in active area of display panel, which makes the flatness of metal layer in GOA region worse. The non-uniformity of thickness of Cu metal film, SiN<i><sub>x</sub></i> film and SiO<sub>2</sub> film around glass substrate lead to the position dependence of the anti-ESD damage ability of IGZO TFT in the GOA region. If there is a transition zone of film thickness change in IGZO TFT with large area, the ESD failure will occur easily. Accordingly, we propose to split large area IGZO TFT into several sub-TFT structures, which can effectively improve the ESD failure.

Low trigger voltage bulk FinFET silicon controlled rectifier in nanotechnology

The bulk fin field-effect transistor (FinFET) has been the primary semiconductor technology in nanotechnology. To protect low supply voltage circuits based on FinFET, trigger voltage [Formula: see text] of the silicon controlled rectifier (SCR) which acts as electrostatic discharge (ESD) protection device should be lowered further. In this paper, in order to lower the [Formula: see text] an extra implant technique is proposed to form bridging well low trigger voltage FinFET SCR (FinFET BRLVTSCR). The experiments demonstrate that the trigger voltage can be lowered effectively. Moreover, the TCAD simulations bring an in-depth physical understanding of ESD current conduction and failure mechanism during ESD protection. Finally, the turn-on characteristic demonstrates proposed novel SCRs are fast and effective under TLP and very fast TLP (VFTLP) stress.

Failure analysis on 14 nm FinFET devices with ESD CDM failure

Electrostatic Discharge (ESD) is an important area for the semiconductor industry because ESD has an impact on production yield and product quality. ESD problems are increasing and have become challenging in the semiconductor industry because of the trends toward higher speed and shrinking in technology node. By continually shrinking the transistor with technology scaling, the process, circuit design, and failure analysis (FA) are getting more challenging. This paper is about FA on a 14 nm Fin-Field Effect Transistor (FinFET) device which has ESD failure after Charged Device Model (CDM) test. In most ESD failure FA, most of the time found Electrical Over Stress (EOS), the important is to understand which process layer or design causing the EOS. At the same time, this paper also discusses the difficulties faced, the FA technique used, the bottleneck of the 14 nm FinFET FA by old technology node FA equipment, and the FA findings. Finally, the ESD failure was identified with Scanning Transmission Electron Microscope (STEM)/Energy Dispersive Spectroscopy (EDS) analysis. The FA findings of the failure are related to the front end of line (FEOL), the metal gate of FinFET was fused with active, and the material in the metal gate was out-diffused.

Micro-Raman spectroscopy applied in crystal structure analysis on the ESD failure mechanism of SiC JBS diodes

This paper propose a novel reliability analysis approach for electrostatic discharge (ESD) stress on 4H-SiC junction barrier Schottky (JBS) diodes using the technology of Micro-Raman spectroscopy. Several conventional analysis are firstly used to determine the failure site after the JBS diodes are destructed by ESD stress, including optical microscope (OM), Photoemission microscopy (PEM) and scanning electron microscopy (SEM). Then, the Micro-Raman spectroscopy is applied to analyze element identification and crystal structure of micro failure site. The analysis reveals that high electric field and high temperature concentrate in the high-voltage termination, resulting in diode burnout and changing the physical microstructure of base SiC. Furthermore, in the micro failure site, 4H-SiC with different Raman spectrum from base 4H-SiC are clearly found, and carbon escapes out from base SiC by combustion, leaving a mixture of amorphous silicon and polysilicon, which is decomposed from the base SiC on the failure surface.

Deep sub-micron ESD GGNMOS layout design and optimization

In the field of integrated circuits, ESD (Electro Static Discharge) has always been a rather serious problem of reliability. Enhanced ESD tolerance of IC chips became a focus of research on IC failure protection design. The thesis is better to solve the multi-fingered non-uniform conduction of ESD devices under electrostatic pulse. Layout parameters DCGS (Drain-Contact to Gate Spacing), SCGS (Source-Contact to Gate Spacing) and BS (Substrate-source spacing) size in the paper can be used as reference for ESD GGNMOS (Gated Ground NMOS) layout design. Also this paper provides setting the DRC (Design Rule Check) command to check the distance between the N+ diffusion regions of different potentials so that ESD failure is prevented effectively. TLP (Transmission Line Pulse) current pulse signal is adopted to measure characteristics of the GGNMOS. The thesis descripts a ESD Optimal layout design from five aspects of introduction, Key elements of ESD circuits layout design, ESD layout optimization, a ESD GGNMOS layout instance and conclusion.

Part II: RF, ESD, HCI, SOA, and Self Heating Concerns in LDMOS Devices Versus Quasi-Saturation

Various LDMOS device design parameters to mitigate quasi-saturation (QS) have been identified. Based on this, a set of independent and mixed device designs to mitigate QS, while maximizing the device performance, are presented. The impact of QS on the analog/RF/switching performance of these independent and mixed designs is investigated thoroughly, while analogizing performance with QS for the first time. Furthermore, hot carrier induced (HCI) degradation in various independent and mixed LDMOS designs is studied using spherical harmonic expansion of Boltzmann transport equation. In addition to this self-heating behavior, safe operating area (SOA) boundaries and electrostatic discharge (ESD) behavior of independent and mixed LDMOS designs with and without QS are studied. For the first time, HCI degradation, self-heating behavior, SOA boundary, and ESD failure in LDMOS devices are correlated with the extent of QS in LDMOS devices, based on which device design guidelines to tackle all performance versus reliability challenges are derived.

Malfunctions of Medical Devices Due to Electrostatic Occurrences Big Data Analysis of 10 Years of the FDA’s Reports

An electrostatic discharge (ESD) event can cause a medical device to fail and pose a threat to patients’safety. This paper presents the data mining analysis of ESD failures in medical devices, over the last ten years, using the U.S. FDA’s manufacturer and user facility device experience database. The most frequent failure modes and activities resulting in ESD events were identified and correlated with key environmental factors. Recommendations are then presented to medical device manufacturers and hospitals.

Case Study on Failure Analysis of Electrostatic Discharge Damage of Semiconductor Devices

The semiconductor device has been widely used in electromechanical products. Electrostatic discharge damage is an important reason for the failure of semiconductor devices, so the electrostatic discharge damage failure analysis plays an important role in determining the reasons for the failure of semiconductor devices and making rectification and improvement measures. Through collecting and analyzing cases of electrostatic discharge failure analysis, the main technology of electrostatic discharge failure analysis and the methods of analyzing electrostatic discharge damage are summarized. The suggestion of electrostatic discharge damage failure analysis is also given.

ESD Robustness Enhancement Study of Ultra-High-Voltage JFET With Ballast Structure

Electrostatic discharge (ESD) robustness improvement of ultra-high-voltage devices is a challenging task. This paper presents an ESD robustness enhancement study of an 800 V junction field-effect transistor (JFET) including a silicon-controlled rectifier (SCR) structure. During a human body model (HBM) event, the fabricated SCR-JFET showed a deep voltage snapback and an unexpectedly high current peak, resulting in an ESD failure due to current filamentation. 3-D TCAD analysis is effectively utilized for ESD enhancement study. First, 3-D HBM simulation reproduces the current filamentation phenomenon and the observed ESD failure. Then, a drain modified SCR-JFET, which includes a p+ ballast region, is studied. TCAD simulations demonstrate ESD robustness improvement with the ballast device and make clear its performance enhancement mechanism. Based on the TCAD study results, the ballast device is fabricated. Photo-emission microscope measurement results clearly show an alleviation of the current filamentation. As a result of HBM tests, we successfully improve HBM robustness from 1.93 kV to 2.63 kV with the ballast structure.

Characteristics of VUV ionizer in a vacuum chamber of flat panel displays

Flat panel displays are often exposed to the electrostatic damage during various panel manufacturing processes. In this paper, we report the electrostatic discharge failure in a unique process condition of OLED display process during which the substrate of OLED display is turned over while in the vacuum chucking condition. In order to solve this failure, we adopted newly developed technology of VUV (Vacuum Ultraviolet) radiation to neutralize the electrostatic electricity. This technology generates ions and electrons by ionizing residual molecules in vacuum chamber such that it enables the charged substrates to be neutralized in the chamber. While this new neutralization method is certainly effective in high vacuum process, the lifetime and performance of the VUV ionizer are not validated. To understand the lifetime and performance of VUV ionizer, we conducted the experiments in the vacuum chamber of an 8th generation display facility with various operating time of UV lamp. We analyzed the characteristic of VUV lamp and suggested the neutralization mechanism of VUV ionizer in a low pressure. Based on the experiments, this new neutralization method performs well under the high vacuum environment and is able to completely reduce the electrostatic potential down to 0 V within a short time.