Electrostatic Discharge Damage Research Articles

ESD Events to Wearable Medical Devices in Healthcare Environments—Part 1: Current Measurements

Wearable medical devices are widely used for monitoring and treatment of patients. Electrostatic discharge can render these devices unreliable and cause a temporary or permanent disturbance in their operation. In a healthcare environment, severe electrostatic discharge (ESD) can occur while a patient, lying down or sitting on a hospital bed with a wearable device, discharges the device via a grounded bedframe. To protect the devices from ESD damage, the worst-case discharge conditions in the usage environment need to be identified. Previous studies by authors revealed that such events could be more severe than the conventional human metal model (HMM). However, the impact of various body postures and device location on the body and the severity of the discharge current compared with HMM have not been investigated for healthcare environments. This study is an attempt to address the gap in the literature by investigating severe discharges in such environments and characterizing their current waveforms for three postures (standing on the floor, sitting, and lying down on a hospital bed), two device locations (hand and waist), and four body voltages (2, 4, 6, and 8 kV). This study highlights that the IEC 61000-4-2 standard may not be sufficient for testing wearable medical devices.

Comparison of ESD Damage Test for Common-Mode Chokes With ESD Gun and TLP-HMM

The method of electrostatic discharge (ESD) damage test for common-mode chokes has been standardized in IEC 62228–5 Annex E. However, there is a concern about the reproducibility of the ESD damage test using the ESD gun described therein. Against this background, the possibility of replacing the ESD gun with a transmission line pulse–human metal model (TLP-HMM) was investigated. The results of the ESD damage test using the ESD gun and TLP-HMM are found to be similar but not exactly the same, especially at low frequencies. Moreover, due to the different waveform generation principles and circuit configurations of the ESD gun and TLP-HMM, even if a load of the same structure is used to calibrate the ESD gun and TLP-HMM, when they are applied to other loads, it is still difficult to guarantee that the discharge currents are the same. The findings raise an issue on how to define a standard TLP-HMM so that it could provide the worst test result compared to the ESD gun.

(Invited) Short Channel Coplanar Amorphous-Indium-Gallium-Zinc-Oxide Thin-Film Transistors on Polyimide Substrate for High Resolution Displays

High-resolution active-matrix organic light-emitting diode (AMOLED) thin-film transistor (TFT) backplane with lower power consumption is needed for augmented reality (AR) applications. The near-to-eye format of AR terminals needs facing several technical challenges, such as higher optical efficiency, wider field of view, lighter weight, and smaller size to accelerate widespread applications. For these reasons, downscaling of TFTs with amorphous-indium-gallium-zinc-oxide (a-IGZO) or LTPS is required. The channel length should be less than 1 μm and the flexible substrate is better than glass because of light weight and very thin structure. TFT technologies on polyimide (PI) substrate can support the applications for foldable and rollable displays. For flexible AMOLED, PI layer of 10 to 20 um is widely used for foldable displays. The PI layer is coated by slot coating on the top of a carrier glass with a buffer layer of carbon nanotubes (CNTs) and graphene oxide (GO) mixture coated by spray. This layer can reduce the adhesion force between PI and glass and thus mechanical detachment can be possible. The CNTs are conducting so that it can release the electrostatic discharge (ESD) damage because CNTs/GO layer exists on the bottom side of the PI substrate. The PI substrate is covered by SiO2 and ZrAlOx layers (five layers in total starting with SiO2) by plasma enhanced chemical vapor deposition and spray pyrolysis, respectively, which acts as a gas barrier. The amorphous ZrAlOx film by spray coating can be used as a high-k gate insulator and also a gas barrier. The threshold voltage of a-IGZO TFTs tends to shift toward negative gate voltage with decreasing the channel length. In this work, a ZrAlOx passivation layer is introduced for the short channel, coplanar a-IGZO TFT. A very thin ZrAlOx layer is deposited by spray pyrolysis on the top of a-IGZO TFT at the substrate temperature of 350 ℃ before interlayer deposition. The a-IGZO TFT with a very thin ZrAlOx layer exhibits the stable threshold voltage dependence with decreasing the channel length. The 0.8 μm channel length a-IGZO TFT with ZrAlOx layer by spray pyrolysis at the substrate temperature of 350 ℃ exhibits the field-effect mobility of 7.09 cm2 V-1 s-1, the threshold voltage of -0.6 V, and on/off current ratio of 3.3 × 107. The formation of Zr-O bonds on the a-IGZO surface region reduces the carrier concentration in the a-IGZO TFT offset region, between source/drain contact and the channel, and blocks the carrier diffusion into the channel. This is the first reported self-aligned coplanar a-IGZO TFT under 1 μm channel length on a flexible substrate. Figure 1

Flexible Amorphous Indium-Gallium-Zinc Oxide Thin-Film Transistor with Aluminum Oxide Gate Insulator on Polyimide Substrate By Spray Pyrolysis for Foldable Display

Research interest in thin-film transistor (TFT)-based flexible electronics for next-generation foldable and rollable displays is increasing, centering on flexible plastic substrates such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyimide (PI). For flexible electronics using plastic substrates, it is important to select suitable semiconductor materials that can be deposited at low substrate temperature. Metal oxide (MO) semiconductors such as indium-gallium-zinc oxide (IGZO), zinc oxide (ZnO) are attracting attention as suitable candidates for plastic substrate electronics because of their higher mobility and optical transmittance than hydrogenated amorphous silicon (a-Si:H). In addition, since it can be processed at a lower temperature than low-temperature polysilicon (LTPS), it can be easily applied to flexible plastic substrates. One of the greatest advantages of MO is that it can be easily fabricated by conventional semiconductor processing methods such as sputtering, atomic laser deposition, and solution processes. Among them, solution-processed deposition method is particularly advantageous in terms of manufacturing efficiency because it does not require a separate vacuum system, and can efficiently utilize raw materials, so the fabrication cost is inexpensive. In particular, spray pyrolysis can guarantee environmental stability, high mobility, and large area production than other solution processes. In this work, we developed the high-performance, flexible a-IGZO/Al2O3 TFTs using spray pyrolysis fabricated on the flexible PI substrate. In a previous study, we developed a method to reduce curling and electrostatic discharge (ESD) damage to PI substrates by using a mixture of carbon nanotubes (CNTs) and graphene oxide (GO) between carrier glass and PI substrate. Therefore, it was possible to mechanically detach the TFTs on PI substrate and handle them easily even after detachment. The spray-pyrolyzed Al2O3 film is one of the high-k dielectric materials, which can lower the operating voltage, so the low-power consumption of the TFT backplane can be realized. The flexible spray-pyrolyzed a-IGZO/Al2O3 TFT exhibits the field-effect mobility (µFE) of 9.75 cm2 V−1 s−1, threshold voltage (VTH) of −0.8 V, subthreshold swing (SS) of 0.29 V dec−1, and on/off current ratio of 6.2 × 107. Even without TFT passivation layer, it shows environmental stability. The TFTs show robust electrical performance even under tensile strain with a bending radius of 1 mm. In addition, it showed stable electrical characteristics even in the repeated bending test of 30,000 cycles under compressive strain with a bending radius of 1 mm. This is due to fewer defects resulting from the smooth interface of the a-IGZO film and the Al2O3 film deposited through spray pyrolysis. Therefore, spray-pyrolyzed a-IGZO/Al2O3 TFT fabricated on PI substrate is a promising candidate for next-generation foldable display application. Figure 1

Forensic Engineering Investigation of Electrical and Electronic Causes of an Industrial Equipment Failure

This case involved industrial equipment whose repeated, seemingly random failures resulted in the buyer of that equipment suing the seller. The failures had been isolated to a group of several transistors within electro-mechanical modules within the equipment, but the root cause of those transistors failing had not been determined. The equipment seller had more than 1,000 units in the field with no similar failures. And the electro-mechanical module manufacturer had more than 20,000 units in the field with no similar failures. Electrical contractors hired by the buyer had measured power quality, and reported no faults found in the three-phase power at the equipment terminals. This paper presents circuit analyses of the failing electro-mechanical module, basics of electrostatic discharge damage and protection, and the root cause of these failures — an electrical code-violating extraneous neutral-to-ground bond in a secondary power cabinet.

Protective Properties of Diamond-like Carbon on Alumite against Electrostatic Discharge Damage

Protective Properties of Diamond-like Carbon on Alumite against Electrostatic Discharge Damage

Novel dual-direction electrostatic discharge device with lateral PNP transistor

With the shrinking of semiconductor technology and the increasing of integrated circuits, electrostatic discharge (ESD) as a common natural phenomenon has become one of the main reasons for the failure and reliability reduction of electronic products in integrated circuits. A novel dual-direction ESD device (PNP_DDSCR) with embedded lateral PNP transistor is proposed for diminishing ESD damage. The response process and current transportation of PNP_DDSCR under different ESD stress modes are investigated. Comparative analyses between conventional DDSCR and PNP_DDSCR are executed by TCAD simulation. On the stage of device triggering, the embedded lateral PNP transistor inner DDSCR system provides triggering current for device. The injection efficiency of parasitic transistor in the DDSCR system is improved, and the positive feedback system is promoted. Thus, the holding voltage of PNP_DDSCR is higher than that of conventional DDSCR. At the same time, an extra triggering path introduced by embedded lateral PNP transistor of PNP_DDSCR makes the total triggering path of device shorten. Therefore, the transient overshoot voltage of PNP_DDSCR is lower than that of DDSCR. For thermal performance, most of the heat first accumulates near the lateral PNP transistor , and then the peak point of heat turns to main SCR path with the conduction of PNP_DDSCR. The heat accumulation in PNP_DDSCR is shared by the path of embedded lateral PNP transistor. As a result, the average temperature in PNP_DDSCR is lower than that in DDSCR and the ability of PNP_DDSCR to dissipate heat is more perfect. Comparing with DDSCR, the conclusions are obtained. Under the condition of transmission line pulse (TLP) test simulation analyses, the triggering voltage is reduced by 31%, the holding voltage is increased by 16.8%, the ESD design window is optimized by 44.5%, and on-resistance is lower. When TLP stress is 2.67 A, the average temperature of PNP_DDSCR is much lower than that of traditional DDSCR in the whole conduction process. With the increase of pulse lasting time, average temperature difference between two devices becomes great further. According to the very fast TLP (VF-TLP) testing results, clamping capability of PNP_DDSCR under transient overshoot voltage is more stable under the condition of fast turn-on speed. When the VF-TLP stress is 0.1 A, the overshoot voltage of PNP_DDSCR device is the 37% of that of DDSCR device while the PNP_DDSCR maintains a relatively fast triggering speed. Thus, the ESD protection capability of PNP_DDSCR is superior.

Protective properties of hydrogenated diamond-like carbon coatings against electrostatic discharge damage

An Electrostatic Discharge (ESD) causes physical defects in electrical devices and lowers their production yield. As electrostatic charge is maintained on insulative surfaces, ESD protection materials, especially surface treatment protection solutions, are in high demand in the electrical industry. Diamond-Like Carbon (DLC) film shows sp3 (insulative) and sp2 (conductive) structures whose resistivity is adjustable to the ESD protection range according to the sp3/sp2 ratio. In this study, two types of hydrogenated DLCs on conductive and non-conductive substrates were prepared by Linear Ion Source and Plasma Immersion Ion Implantation. The protective properties against ESD, such as resistance and the slow discharge behavior of DLCs on metal and insulative substrates, as well as their tribological properties and structure, were investigated. It was shown that DLCs on insulative materials exhibit good and slow discharge properties to protect electrical devices from ESD damage. The promotion of DLCs in the semiconductor industry could be an excellent solution to raise production yield due to their provision of ESD protection and their good tribological properties.

ESD Diode Protection Incorporated on Leadframe Package

With the new die technology becomes smaller and thinner, silicon die circuit metallization also becomes smaller, thus electronic devices like quad-flat no-leads multi-row (QFN-mr) semiconductor leadframe package design become more sensitive and prone to electrostatic discharge (ESD) damages. This paper focused and introduced an additional surface mount technology by attaching diodes before and after diebonding process to protect the whole package and to prevent package related issues encountered. With this diode attached on the silicon die and leads, added protection could be achieved on the integrated circuit (IC) mounted on the circuit board level.

Design of High-Voltage-Tolerant Power-Rail ESD Protection Circuit for Power Pin of Negative Voltage in Low-Voltage CMOS Processes

In the implanted biomedical devices, the silicon chips with monopolar stimulation design have been widely applied. To protect the negative-voltage pins of the implanted silicon chip from the electrostatic discharge (ESD) damage, the ESD protection circuit should be carefully designed to avoid any wrong current path under normal circuit operation with the negative voltage. In this article, a new power-rail ESD clamp circuit for the application with an operating voltage of −6 V has been proposed and verified in a 0.18- $\mu \text{m}$ 3.3-V CMOS process. The proposed circuit, realized with only 3.3-V nMOS/pMOS devices, is able to prevent the gate-oxide reliability issue under this −6-V application. With the proposed ESD detection circuit, the turn-on speed of the main ESD clamp device, which is a stacked-nMOS (STnMOS), can be greatly enhanced. The STnMOS with a width of $400~\mu \text{m}$ can sustain over 8-kV human body model (HBM) ESD stress and perform low standby leakage current of ~5.4 nA at room temperature under the circuit operating condition with −6-V supply voltage.

ESD protection circuit for V-band RF applications in a 65nm CMOS technology

To apply radio frequency circuits, nanoscale CMOS technologies are greatly used but this consequence to a thinner gate oxide and silicided drain/source. With this, the electrostatic discharge (ESD) robustness of RF circuits will be much more degraded. Therefore, there is a need for an ESD protection circuit design in RF circuits against ESD damages. In this paper, the proposed ESD protection circuit is presented with concept based silicon-controlled rectifier (SCR) device, two diodes, PMOS transistor and an inductor to efficiently provide protection for radio-frequency (RF) circuits from ESD damages in nanoscale CMOS process. The concept based SCR device is aided with an inductor to provide efficient ESD path discharge to the SCR device. Moreover, the inductor is used to resonate out the parasitic capacitance generated by the ESD protection circuit at the preferred frequency. In addition, the proposed ESD protection circuit is implemented to a low noise amplifier (LNA) at 60-GHz frequency within an efficient area. Furthermore, the ESD protection circuit is simulated to achieve over 2-kV human body model ESD robustness with good RF performances on LNA in 65-nm CMOS technology.

ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains

To effectively protect the interface circuit between separated power domains from electrostatic discharge (ESD) damage, a new diode-triggered quad-silicon-controlled rectifier (DTQSCR) is proposed and realized in a 0.18- $ {\mu }\text{m}$ 1.8-V/3.3-V CMOS process. Since the DTQSCR embeds four silicon-controlled rectifier paths and a structure of back-to-back diodes, the silicon area can be efficiently reduced more than 30% as compared to the traditional ESD protection design under the same ESD specification. From the measurement results in silicon chip, an interface circuit (level shifter) with the proposed ESD protection design can successfully sustain a human-body-model of greater than 5.5 kV. The proposed ESD protection device is suitable to protect the interface circuits between different power domains.

Test Scheme and Degradation Model of Accumulated Electrostatic Discharge (ESD) Damage for Insulated Gate Bipolar Transistor (IGBT) Prognostics

This paper develops a degradation test scheme for insulated gate bipolar transistors (IGBTs) that are subjected to repeated electrostatic discharge (ESD). The proposed 7-step scheme is implemented to characterize the latent ESD damage of trench gate field stop IGBTs. An empirical degradation model based on the shift in threshold voltage is proposed with three model parameters: two parameters are IGBT-type-dependent and the other parameter is manufacturer-dependent. The two IGBT-type-dependent parameters for trench gate field stop IGBTs are determined using the test results obtained from two types of IGBT components produced by the same manufacturer. The correlation between the model and the test data is extremely high, which proves the accuracy of the proposed model. The applicability of the model is further corroborated using the test data obtained from IGBT components and modules produced by other manufacturers. The results confirm that the proposed degradation model can accurately predict the degradation of IGBT components as well as modules subjected to ESD damage.

Full-Wave Simulation of System-Level Disruption During Secondary ESD Events in a Smartphone

To demonstrate the electromagnetic full-wave simulation of a secondary electrostatic discharge (ESD), an ESD generator is modeled in three dimensions (3D) and in contact mode discharging to a non-grounded, metallic ear-mesh of a smartphone. The nonlinear Rompe–Weizel SPICE model computes the arc resistance of the secondary discharge between ungrounded metal and a grounded enclosure. The SPICE model is solved using a circuit simulator, and the 3-D model is solved using the transmission-line matrix time-domain numerical method. Transient cosimulation is a new technique that is used to solve both circuit and 3-D models at the same time. The simulation predicts the coupling from ESD to a victim trace in the smartphone. Measurements performed at several stages validate the simulation results. Using this novel methodology, the user can simulate the secondary discharge in products to predict ESD damage and disruption on a system level.

Electro-static discharge protection analysis and design optimization of interlayer Cu interconnection in InGaZnO thin film transistor backplane

The InGaZnO thin film transistor (IGZO TFT) backplane combined with Cu interconnection has nearly an order of magnitude lower in the ability to withstand voltage than that of traditional a-Si TFT backplane on the production line. The breakdown voltage of Mo/Cu interconnection between data line and gate line is only about 60% of that of traditional a-Si TFT backplane. The electrostatic discharge (ESD) breakdown of Mo/Cu:SiN<sub><i>x</i></sub>/SiO<sub>2</sub>:Mo/Cu structure has become an important factor affecting the normal display of IGZO TFT ultra high definition (UHD) panel. We find that the anti-ESD damage ability of IGZO TFT devices needs matching with the anti-ESD damage ability of interlayer Cu interconnection in order to achieve a high-robustness IGZO TFT backplane. The position of ESD damage in IGZO TFT backplane is commonly in the climbing place where the data line crosses the scanning line. In this paper, a Cu diffusion model is proposed to explain the mechanism for the ESD failure of interlayer Cu interconnection. The Cu metal in gate line diffuses into SiN<sub><i>x</i></sub>/SiO<sub>2</sub> gate insulator, and Cu metal at the corner of data line, where the date line crosses the gate line, diffuses into SiO<sub>2</sub> film on the date line. The selection conditions of three kinds of protection architectures for ESD protection circuits around Cu interconnection, i.e. R-type, R-half-type, and Diode-type protection architectures, are proposed. On the basis of process optimization such as Cu metal film forming and Cu metal interface treatment, an ESD protection method for the Cu interconnection periphery of IGZO TFT backplane with high robustness is proposed. For the stable production process of IGZO TFT, combined with the design window of ESD protection circuit, the peripheral ESD protection circuit of Cu interconnect is designed with diode-type protection circuit on the IGZO TFT backplane of large-sized UHD and QUHD panel, which effectively improves the effect of interlayer Cu interconnection of IGZO TFT backplane on ESD damage. Through the production verification, it is proved that the metal diffusion of Cu interconnection on IGZO TFT backplane is the fundamental reason for reducing the anti-ESD damage ability of Mo/Cu:SiN<sub><i>x</i></sub>/SiO<sub>2</sub>:Mo/Cu structure. The rationality of the proposed ESD damage model for interlayer Cu interconnection is verified, which provides a theoretical basis for subsequent IGZO TFT backplane design with high robustness.

Electro-static discharge failure analysis and design optimization of gate-driver on array circuit in InGaZnO thin film transistor backplane

There is a risk of InGaZnO thin film transistor (IGZO TFT) failure, especially electro-static discharge (ESD) damage of gate driver on array (GOA) circuits, due to the combination of Cu interconnect, InGaZnO (IGZO) active layer and SiN<i><sub>x</sub></i>/SiO<sub>2</sub> insulating layer used to realize large-scale ultra-high resolution display. It is found that the IGZO TFT damage position caused by ESD occurs between the source/drain metal layer and the gate insulator. The Cu metal of gate electrode diffuses into the gate insulator of SiN<sub><i>x</i></sub>/SiO<sub>2</sub>. The closer to the ESD damage area the IGZO TFT is, the more serious the negative bias of its threshold voltage (<i>V</i><sub>th</sub>) is until the device is fully turned on. The IGZO TFT with a large channel width-to-length ratio(<i>W</i>/<i>L</i>) in GOA circuit results in a serious negative bias of threshold voltage. In this paper, the ESD failure problem of GOA circuit in the IGZO TFT backplane is systematically analyzed by combining the ESD device level analysis with the system level analysis, which combines IGZO TFT device technology, difference in metal density between GOA region and active area on backplane, non-uniform thickness distribution of gate metal layer and gate insulator and so on. In the analysis of ESD device level, we propose that the diffusion of Cu metal from gate electrode into SiN<sub><i>x</i></sub>/SiO<sub>2</sub> leads to the decrease of effective gate insulator layer, and that the built-in space charge effect leads to the decrease of the anti-ESD damage ability of IGZO TFT. In the analysis of ESD system level, we propose that the density of metal layers in GOA region is 4.5 times higher than that in active area of display panel, which makes the flatness of metal layer in GOA region worse. The non-uniformity of thickness of Cu metal film, SiN<i><sub>x</sub></i> film and SiO<sub>2</sub> film around glass substrate lead to the position dependence of the anti-ESD damage ability of IGZO TFT in the GOA region. If there is a transition zone of film thickness change in IGZO TFT with large area, the ESD failure will occur easily. Accordingly, we propose to split large area IGZO TFT into several sub-TFT structures, which can effectively improve the ESD failure.

A wireless and wearable measurement system for human body electrostatic monitoring application

In particular, electrostatic discharge (ESD) and electric overstress (EOS), for the production assembly, were concluded as the common problems for all electronic manufacturers in worldwide. Uncontrollable and invisible electrostatic discharge events were the major problems, because production quality was performed by well-controlled electrostatic discharge and electric overstress. Currently, it was passively managed the electrostatic grounding path by a connection on the assembly line, the correct wearing of electrostatic ground wrist/ankle straps, and the installation of static ionizers on top of the riskiest workstations to dissipate the electrostatic energy, with the regular check of electrostatic discharge being eliminated or dissipated by static ionizers. The above methods could merely detect fixed locations, but could not real time detect the electrostatic conditions of an operator and record the related events for the database analysis. In order to improve the above issue, the study proposed a wearable and wireless human body electrostatic monitoring system to real-time detect the ESD event of an operator and record the ESD events for the database analysis. By using the real-time alert mechanism, the proposed system could effectively prevent these ESD damages: (1) could inform the operator to immediately discharge the cumulative electric charge; (2) could be transmit to the back-end host system via Bluetooth to make up the careless mistake in the operation, and this alert could be regarded as the second prevention; (3) could be recorded in database for successive data analyses. Finally, the proposed system was also validated and applied in the production assembly and the experimental results indicated that it could exactly provide an effective way to reduce the influence of ESD/EOS.

Case Study on Failure Analysis of Electrostatic Discharge Damage of Semiconductor Devices

The semiconductor device has been widely used in electromechanical products. Electrostatic discharge damage is an important reason for the failure of semiconductor devices, so the electrostatic discharge damage failure analysis plays an important role in determining the reasons for the failure of semiconductor devices and making rectification and improvement measures. Through collecting and analyzing cases of electrostatic discharge failure analysis, the main technology of electrostatic discharge failure analysis and the methods of analyzing electrostatic discharge damage are summarized. The suggestion of electrostatic discharge damage failure analysis is also given.

Design of 2.4-GHz T/R switch with embedded ESD protection devices in CMOS process

As CMOS processes advanced, the integration of radio-frequency (RF) integrated circuits was increasing. In order to protect the fully-integrated RF transceiver from electrostatic discharge (ESD) damage, the transmit/receive (T/R) switch of transceiver frond-end should be carefully designed to bypass the ESD current. This work presented a technique of embedded ESD protection device to enhance the ESD capability of T/R switch. The embedded ESD protection devices of diodes and silicon-controlled rectifier (SCR) are generated between the transistors in T/R switch without using additional ESD protection device. The design procedure of RF circuits without ESD protection device can be simplified. The test circuits of 2.4-GHz transceiver frond-end with T/R switch, PA, and LNA have been integrated and implemented in nanoscale CMOS process to test their performances during RF operations and ESD stresses. The test results confirm that the embedded ESD protection devices can provide sufficient ESD protection capability and it is free from degrading circuit performances.

Nondestructive fault localization of IC interconnection by using ultrasonic heating

A nondestructive method of ultrasonic fault localization of IC interconnection without mold decapsulation was proposed instead of the optical-beam-induced resistance change (OBIRCH) method. The signal principle of the proposed method is based on the resistance change induced by local ultrasonic heating. To investigate the principle, numerical analysis constructed by sound and temperature field simulations is carried out and its results were compared with experimental results. The sound field is calculated by Fourier analysis. The temperature field is discretized using an equivalent thermal network circuit. Numerical simulation results show a good agreement with experimental results, suggesting that the signal in the proposed method was induced by ultrasonic heating. Moreover, ultrasonic heating induced the signal of the proposed method in a sample covered with commercially available resin including fillers (average diameter: 16 µm), and electro-static discharge (ESD) damage was localized by ultrasonic heating without mold decapsulation. These results suggest that the signal induced by ultrasonic stimulation is detectable and available for use in analysis.