Electrostatic Chuck Research Articles

Influence of the Surface Topography on the Micromechanical Properties and Performance of a CMP Finished AlN Component for Silicon Plasma Etching

A microtibological study of the effect of the CMP machining surface damages (SD) on the micromechanical properties of AlN electro-static chuck (ESC) for silicon plasma etching is presented. AFM and SEM examinations of the AlN ESC, which were CMP finished to a surface roughness, Ra = 20 nm, have revealed machining geometry errors and chemical mechanical SD caused by the CMP slurry. The elastic modulus (E) and hardness (H) of AlN and those of yttrium (Y) particles were discretely clarified using localized nanoindentation technique. The results showed that the CMP machining SD fatally affected the AlN/Y boundary strength and resulted to errors in the first contact points between the indenter and the sample. In addition to SD, the micro scale viscoelasticity phenomena of AlN in indentation caused peculiarities at peak loads in the load vs. depth plots. Under these circumstances, the values of E and H measured using Oliver and Pharr's method are in fact underestimated; E = 400 GPa and H = 20 GPa for AlN particles, 300 GPa and 17 GPa for Y particles and 500 GPa and 16 GPa for AlN/Y interface, respectively.

Low-thermal expansion electrostatic chuck materials and clamp mechanisms in vacuum and air

Low-thermal expansion electrostatic chuck materials have been evaluated for use in the EUVL α-tool of ASML because of the requirements for overlay and critical dimensions. The material investigated showed clear capacitive Coulomb clamping behavior, giving a maximum pressure of 1.04 bar. In vacuum, the limitation to the maximum pressure is the spontaneous field emission of electrons across the gap between wafer and dielectric material. In dry air, the actual voltage over the air-filled gap limits the maximum pressure because of electrical breakdown (Paschen curve minimum). The humidity in normal air further decreases the pressures obtained. Model clamps and test set-ups were designed and manufactured by TNO TPD.

Generation mechanism of residual clamping force in a bipolar electrostatic chuck

Clamping and residual clamping forces of a Johnsen–Rahbek-type (JR-type) bipolar electrostatic chuck (ESC), which has electrically independent dual electrodes, were measured. Area ratios of the ESC’s two electrodes ranged from 1 to 4.6. It was found that the clamping force per unit area decreases with increasing area ratio and that the residual clamping force per unit area increases with increasing area ratio. To reveal the mechanism of residual clamping force, an equivalent circuit model of a JR-type bipolar ESC was devised. The model showed that the residual clamping force is caused by the residual charge that results from the charge difference in two monopolar ESCs. The charge difference is due to the resistance dependency on voltage of the dielectric layer of the ESC. The wafer voltage calculated from the model agreed well with the voltage measured by an electrostatic voltmeter. It can be concluded that the model is suitable for simulating the performance of a bipolar ESC.

Extreme ultraviolet lithography mask flatness and electrostatic chucking analysis

The Semiconductor Industry Association Roadmap for Extreme Ultraviolet Lithography (EUVL) calls for significant improvements in the quality and flatness of the substrate and patterned mask. Due to the difficulty of meeting the mask flatness specifications, an alternative strategy has been proposed to ensure that suitable substrates will be available for EUVL. A new SEMI standard for EUVL electrostatic chucks is currently being developed. If such a standard were established, then the flatness requirements for the substrate might be relaxed to permit certain types of bow that can later be flattened by the chuck. The purpose of this study is to identify which shapes can indeed be flattened by an electrostatic chuck. To support the proposed strategy, it is essential that the clamping ability of the electrostatic chuck be characterized and well-understood. The ability of the chuck to flatten the mask will depend primarily on the mechanical stiffness of the chuck and the clamping pressure. Legendre polynomials have been identified as an effective and efficient means of representing EUVL mask surface shapes. Finite element (FE) models have been developed to utilize the Legendre polynomials as input data to define the surfaces of the reticle. The FE models were then used to determine the clamping response of the various mask shapes. In particular, the maximum reticle-to-chuck gap within the flatness quality area and over the entire reticle has been tracked as a function of clamping pressure and chuck thickness for the low-order Legendre modes.

Real-time control of ion density and ion energy in chlorine inductively coupled plasma etch processing

In this study, we have experimentally demonstrated the real-time closed-loop control of both ion density and ion energy in a chlorine inductively coupled plasma etcher. To measure positive ion density, the trace rare gases-optical emission spectroscopy is used to measure the chlorine positive ion density. An rf voltage probe is adopted to measure the root-mean-square rf voltage on the electrostatic chuck which is linearly dependent on sheath voltage. One actuator is a 13.56 MHz rf generator to drive the inductive coil seated on a ceramic window. The second actuator is also a 13.56 MHz rf generator to power the electrostatic chuck. The closed-loop controller is designed to compensate for process drift, process disturbance, and pilot wafer effect and to minimize steady-state error of plasma parameters. This controller has been used to control the etch process of unpatterned polysilicon. The experimental results showed that the closed-loop control had a better repeatability of plasma parameters compared with open-loop control. The closed-loop control can eliminate the process disturbance resulting from reflected power. In addition, experimental results also demonstrated that closed-loop control has a better reproducibility in etch rate as compared with open-loop control.

Simulation model of in-plane distortion in extreme ultraviolet lithography mask during chucking without friction

In-plane displacement (IPD) of an extreme ultraviolet lithography (EUVL) mask in a flat state during the electrostatic chucking stage without friction is examined through simulations. For predicting IPD of an EUVL mask, a simulation model based on two-dimensional plane stress theory is developed. With regard to the absorber patterns both square and rectangle, film stress and absorber coverage dependency of IPD is investigated. Mitigation of IPD to the 1-nm level is possible by reducing absorber stress to ±100 MPa. The change in surface height caused by absorber film stress of ±500 MPa is less than 1 nm. The influence of change in surface height on image placement shift was found to be negligible because the image placement shift is 0.03 nm.

Effect of carbon enrichment induced by photoresist on highly selective SiO2 etching

We propose two models to discuss the behavior of the selective etching of SiO2 to the underlying Si3N4 with changing wafer surface temperatures. For this investigation, three specimens, SiO2, Si3N4, and poly-Si, which are nonpatterned, photoresist-patterned, and poly-silicon-patterned, respectively, have been etched in a surface wave plasma system equipped with an electrostatic chuck for wafer temperature control. The coolant temperature, which controls the wafer temperature, has been changed from −20 to 50 °C. For the nonpatterned wafer, the etch rates of SiO2, Si3N4, and poly-Si increase and the selectivities decreases with wafer temperature. However, for the samples patterned with either photoresist or poly-Si, the etch rates of SiO2 decrease with wafer temperature. The temperature rise also leads to an enhancement of selectivity of SiO2/Si3N4, and the steeper profile angles. The presence of a masking layer, even for the poly-Si-patterned samples, results in a different etching behavior. This is because the sticking probability of the polymer precursor becomes smaller on the sidewall of the profile with the temperature increase. Therefore the thickness of polymer on the sidewall of the contact hole decreases, and the thickness of polymer on the bottom increases as the wafer temperature goes up. Comparing photoresist-patterned samples with poly-Si-patterned ones, we can corroborate the role of the photoresist mask layer, which provides a higher carbon-to-fluorine ratio at the near surface. The carbon enrichment accelerates more steeply the etch rate decrement of the substrate layer. In summary, there are two main contributions attributed by the substrate temperature: changing the sticking coefficient of the fluorocarbon precursor and enhancing the photoresist erosion.

Wafer temperature measurements during dielectric etching in a MERIE etcher

Using both chemical phase change and wireless thermistor temperature measurement techniques, wafer temperatures were measured during plasma processing in a MERIE dielectric etch tool. An inorganic low-k dielectric etch process was studied first, and many parameters were varied to determine their effect on wafer temperature. Wafer temperature rose rapidly when the plasma was turned on, approaching a stable temperature after about 30 s. When the lower electrode temperature setpoint or the rf power setting was increased, wafer temperature increased linearly. Wafer temperature decreased as backside He cooling pressure was increased. A dual-zone electrostatic chuck allowed separate control of center and edge He pressure, and these pressures were varied individually or together. Temperature measurements indicated that the zones give reasonably independent control of center and edge wafer temperature. Wafer temperature throughout a complete organic low-k dielectric stack etch process was also measured.

Fundamental study of an electrostatic chuck for silicon wafer handling

Mechanical holding systems of a wafer might cause serious problems in the semiconductor industry. Electrostatic wafer handling might be one of the possible solutions for such problems. The authors have investigated an attractive force on a silicon wafer by using an electrostatic chuck which consists of interdigitated electrodes and a dielectric thin film. Electrostatic attractive force increases as the applied voltage increases, and with a thinner dielectric layer. With the narrower width and spacing of interdigitated electrodes, the stronger electrostatic force is obtained. When 1-mm width and spacing interdigitated electrodes and 50-/spl mu/m-thick polymer film are used, the strongest force obtained was about 17 N in the vertical direction at 3.5 kV, for a 4-in silicon wafer. When DC high voltage is used, some residual force remains, even after the applied voltage is removed. This was overcome by using variable-frequency AC high voltage.

Electrostatic chuck behaviour at ambient conditions

For advanced lithography applications, high-precision electrostatic chucks with diameters up to 12 inch are being developed at IOF. Although electrostatic chucking is mostly used in vacuum, the principle also works at ambient conditions. However, forces exerted to the wafer may not be the same in both cases. To quantify the influence of environmental conditions, electrostatic forces for various chuck dielectrics were measured under ambient conditions (humid air), dry nitrogen and in vacuum. The forces are found to be significantly reduced at ambient conditions as compared to the vacuum case. When flushing with dry nitrogen, the vacuum level is essentially retained. Clearly, water at the chuck-to-wafer interface reduces the chucking force. We suspect that dissociation of water occurs, entailing ionic charge transport and trapping in the dielectric. This eventually shields the wafer from the chuck electrode.

Recent Progress in Industrial Applications of CAT-CVD (Hot-Wire Cvd)

AbstractRapid progresses are achieved in catalytic CVD (Cat-CVD), often called hot-wire CVD, in the past 3-years NEDO national project in Japan. Cat-CVD technology presents many advantages in thin-film formation processes; high-efficiency of gas use, large-area deposition, no ion bombardment and low-temperature deposition even below 200°C. All of the elemental techniques for the industrially applicable Cat-CVD apparatuses, such as the suppression of the metal contamination, the precise control of the substrate temperature, the life extension of the catalyzer, 1-m size uniform deposition and the chamber cleaning, have been completely developed. Sophisticatedly designed substrate holder with electrostatic chuck and showerhead equipped with catalyzers are both key technologies for these achievements. High reproducibility for film properties is also obtained by controlling the reaction between high-density radicals and chamber walls. Prototype mass-production apparatus for SiNx passivation films in GaAs devices has been already developed and this will be probably the first application of Cat-CVD in industry. These recent movements appear to promise the drastic revolution in semiconductor and flat-panel display industries by introducing Cat-CVD in very near future.

Simulating the response of electron-beam projection lithography masks under standardized mounting techniques

The mounting standard based upon a proposed four-pad electrostatic chuck for the 200 mm PREVAIL and SCALPEL® masks was assessed to support the electron-beam projection lithography (EPL) mask standardization process. Using numerical simulations, comparative studies were performed to investigate the mask response during fabrication, pattern transfer, and mounting, employing the IBM Falcon/Nighteagle layout as a pattern-specific design for both EPL masks. The results indicated that consistent mounting schemes in the e-beam writer and exposure tool minimized the in-plane distortion (IPD). The proposed chucking configuration appeared to be robust for both EPL technologies for controlling IPD. With additional support enhancement beneath the major strut across the center of the grillage area of the mask, the IPD can be reduced to negligible values.

Development of Cat-CVD apparatus — a method to control wafer temperatures under thermal influence of heated catalyzer

In the catalytic chemical vapor deposition (Cat-CVD) method, a heated metal wire is often used as the catalyzer to crack the process gas molecules. Therefore, the temperature of the wafer near the catalyzer is influenced by heat from the catalyzer. Thus, a special technique is needed to control the wafer temperature. We examined this matter from the viewpoint of the apparatus. The electrostatic chuck (ESC) is employed in the wafer holder for the Cat-CVD apparatus for the first time. The effects of ESC on the temperature control of Si and GaAs wafers are studied in detail for various process conditions. A drastic improvement is obtained in the control of the wafer temperature using ESC.

Electrostatic chucks for lithography applications

High precision electrostatic chucks with diameters up to 12 inches are being developed at IOF for electron/ion-beam lithography applications. For optimal performance, selection of the appropriate chuck dielectric is crucial. We have tested various materials, including sapphire, quartz and glass-ceramics with respect to chucking force under vacuum conditions. Differences in electrostatic force of more than an order of magnitude were observed and are attributed to Coulomb and Johnsen–Rahbek behaviour. For the former, reasonable agreement with theoretical calculations was obtained when taking the corresponding dielectric constants and a finite gap between wafer and support into account. Time constants for chucking and dechucking were determined for the latter.

Sensitive End-Point Detection for Dielectric Etch

A method is described for detecting the initial exposure of the stop layer underlying a patterned dielectric film. The bias compensation signal from the power supply of the ceramic electrostatic chuck displays a step increase when the etch front reaches the underlayer. The end-point signal strength is essentially independent of exposed oxide area over the range ∼0.01 to 1%. End point is detected just as the underlayer is exposed, significantly earlier than that for optical emission end point. The proposed origin of the bias compensation end-point signal is the change in resistance between wafer substrate and plasma as holes are etched through the dielectric film. This model correctly predicts which etch applications will produce an end-point signal, including standard via etch and contact etch. Dual damascene via etch also produces a useful end-point signal, apparently due to lowered resistance of the silicon nitride stop layer during etch. The use of bias compensation end point in a commercial wafer production facility is described. © 2001 The Electrochemical Society. All rights reserved.

Improvements in wafer temperature measurements

Accurate and repeatable wafer temperature measurement and control is critical in many semiconductor processing applications. Many of these applications are done at moderate pressures (0.5–2 Torr) where thermal contact resistance between the wafer and a contact temperature probe is high, and could vary wafer to wafer. The result is an unpredictable difference between the actual wafer temperature and contact measurement probe due to heat transfer across this interface from exothermic reactions, hot plasma gases, or radiant heating. In some applications, this temperature difference is so great that backside helium cooled electrostatic chucks are used to minimize this effect. In many applications, the use of this type of solution is not practical but accurate and repeatable wafer temperature measurement is still required. A new temperature sensor has been developed that utilizes gas injection through a pinhole in a thermocouple pad that creates a “microenvironment” between the pad and the wafer. This results in reduced thermal contact resistance, and more accurate and repeatable temperature measurement. Temperature data on the operation of this probe will be presented, verifying the robustness of this probe. Additionally, diffuse reflectance spectroscopy will be used as a noncontact temperature measurement technique to corroborate data from the new gas-cushion thermocouple.

Fundamental characteristics of electrostatic wafer chuck with insulating sealant

In the semiconductor industry, many manufacturing processes, such as CVD or dry etching, are performed in vacuum condition. The electrostatic wafer chuck is the most preferable handling method under such circumstances. It enables retention of a wafer flat and enhanced heat transfer through the whole surface area because the wafer can firmly contact with the chuck. We have investigated the fundamental study of an electrostatic chuck with comb type electrodes and a thin dielectric film. In order to remove the air gap between them, silicone oil is used as a filler to prevent breakdown. The experimental results proved the potential to use the electrostatic chuck for silicon wafer handling. There, however, is a problem which comes from using silicone oil as an insulating filler. The thin dielectric film is easily deformed by tension when the object starts moving. In this report experimental results of the electrostatic wafer chuck are shown when insulating sealant, instead of silicone oil, is used. The electrostatic force acting on the 4 inch silicon wafer is examined with several types of sealant and dielectric films. The electrostatic force increased with the square of the applied voltage for lower voltage and gradually saturated at higher voltage, and the maximum force obtained was approximately 30 N.

Wafer temperature measurement in PVD systems using the Co–Si reaction

It is becoming increasingly important to control the wafer temperature during IC processing, e.g. PVD. To measure the wafer temperature in PVD systems it is possible to use the Co–Si reaction. The difference in sheet resistance of the Co–Si phases, which form at different temperatures, is used to measure maximum wafer temperature in a PVD chamber. The maximum wafer temperature and the time it takes to reach this temperature are determined by the heat transfer between wafer and chuck. Wafer temperature measurements have been performed using different clamping configurations. Spring clamping of wafers and electrostatic chucks give the best results.

Modeling of the sheath and the energy distribution of ions bombarding rf-biased substrates in high density plasma reactors and comparison to experimental measurements

In plasma etching and deposition processes, the energy distribution of ions incident onto the substrate strongly affects the surface reactions and the film deposition and etching rates. The magnitude and frequency of the rf-bias power applied to the substrate electrode determines the spatiotemporal variations of the sheath potentials and hence the energy distribution of the ions impinging upon the substrate. A self-consistent dynamic model of the sheath, capable of predicting ion energy distributions impinging on a rf-biased electrode, was developed. The model consists of equations describing the charge transport in the sheath coupled to an equivalent circuit model of the sheath to predict the spatiotemporal charge and potential distributions near the surface. Experimental measurements of the energy distributions of ions impinging on a rf-biased electrostatic chuck have also been made in a high density transformer coupled plasma reactor through Ar and Ne plasmas. The predicted ion energy distributions and sheath profiles are in very good agreement with the experimental measurements.

Influence of wafer’s back-surface finish on dry-etching characteristics

Process tolerance and controllability requirements have become more severe with device scaling down and increased integration. The finish of a wafer’s back surface is a factor that affects process conditions for dry etching and rapid thermal annealing. The correlation between back-surface roughness and dry-etching characteristics was investigated. The back-surface roughness was changed from 0.34 nm (rms) to 66.7 nm by final back-surface treatment such as mechanical–chemical polishing or chemical etching. Contact-hole etching with CHF3 gas was performed for interlayer chemical vapor deposited oxide on the front surface of wafers. The etching rate for a smooth back surface (0.34 nm) was increased by 1.1 times over that for a rough back surface (66.7 nm). During contact-hole etching, the wafer temperature of the smooth back surface was 10 °C lower than that for a rough back surface. This is due to the difference in electrostatic chucking force (rms=85–125 nm) during contact-hole etching. When the wafer with ...