Electronic System Level Design Research Articles

A fast MPSoC virtual prototyping for intensive signal processing applications

Due to the growing computation rates of intensive signal processing applications, using Multiprocessor System on Chip (MPSoC) becomes an incontrovertible solution to meet the functional requirements. Today, Electronic System Level (ESL) design is considered a vital premise to overcome the design complexity intrinsic in the heterogeneity of these devices. However, the development of tools at the system level is in the face of extremely challenging requirements such as the rapid system prototyping, the accurate performance estimation, and the reliable design space exploration (DSE).Focusing on the issue of ESL development tools, this paper describes an MPSoC environment design which targets the Multidimensional Intensive Signal Processing (MISP) application domain. Within this environment, we have defined first a generic execution model that supports any type of MPSoC. It can adapt to any parallel application and handle efficiently the scheduling and synchronizations at all the levels of granularity. Second, a new Virtual Processor (VP) based simulation technique is proposed for implementing the execution model. This proposal leverages the high-level specification of the system to provide a heterogeneous MPSoCs simulation without using an Instruction Set Simulator (ISS). VP-based simulation is implemented in SystemC at a timed transactional level allowing a good trade-off between high simulation speed and performance estimation accuracy. The usefulness and the effectiveness of our MPSoC environment is illustrated through two MISP applications executed on a typical MPSoC. Results show that our approach enables fast MPSoC virtual prototyping, data transfers and timing analysis, and reliable DSE for architectural optimizations.

A Multi-Granularity Power Modeling Methodology for Embedded Processors

With power becoming a major constraint for multiprocessor embedded systems, it is becoming important for designers to characterize and model processor power dissipation. It is critical for these processor power models to be useable across various modeling abstractions in an electronic system level (ESL) design flow, to guide early design decisions. In this paper, we propose a unified processor power modeling methodology for the creation of power models at multiple granularity levels that can be quickly mapped to an ESL design flow. Our experimental results based on applying the proposed methodology on the OpenRISC and MIPS processors demonstrate the usefulness of having multiple power models. The generated models range from very high-level two-state and architectural/instruction set simulator models that can be used in transaction level models, to extremely detailed cycle-accurate models that enable early exploration of power optimization techniques. These models offer a designer tremendous flexibility to trade off estimation accuracy with estimation/simulation effort.

A QEMU and SystemC-Based Cycle-Accurate ISS for Performance Estimation on SoC Development

In this paper, we present a fast cycle-accurate instruction set simulator (CA-ISS) for system-on-chip development based on QEMU and SystemC. Even though most state-of-the-art commercial tools have tried very hard to provide all the levels of details to satisfy the different requirements of the software designer, the hardware designer, and even the system architect, the hardware/software co-simulation speed is dramatically slow when co-simulating the hardware models at the register-transfer level (RTL) with a full-fledged operating system (OS). Our experimental results show that the combination of QEMU and SystemC can make the co-simulation at the CA level much faster than the conventional RTL simulation, even with a full-fledged operating system up and running. Furthermore, the statistics indicate that with every instruction executed and every memory accessed since power-on traced at the CA level, it takes 28m15.804s on average to boot up a full-fledged Linux kernel, even on a personal computer. Compared to the kernel boot time reported by Xilinx and SiCortex, the proposed CA-ISS is about 6.09 times faster compared to “SystemC without trace” of Xilinx and about 30.32 times faster compared to “SystemC models converted from RTL” of SiCortex. The main contributions of this paper are threefold: 1) a hardware/software co-simulation environment capable of running a full-fledged OS at the early stage of the electronic system level design flow at an acceptable simulation speed is proposed; 2) a virtual platform constructed using the proposed CA-ISS as the processor model can be used to estimate the performance of a target system from system perspective, which all the previous works, such as QEMU-SystemC, do not provide; and 3) such a virtual platform also provides the modeling capability from the transaction level down to the CA level or the other way around.

Coroutine-Based Synthesis of Efficient Embedded Software From SystemC Models

SystemC is a widely used electronic system-level (ESL) design language that can be used to model both hardware and software at different stages of system design. There has been a lot of research on behavior synthesis of hardware from SystemC, but relatively little work on synthesizing embedded software for SystemC designs. In this letter, we present an approach to automatic software synthesis from SystemC-based on coroutines instead of the traditional approaches based on real-time operating system (RTOS) threads. Performance evaluation results on some realistic applications show that our approach results in impressive reduction of runtime overheads compared to the thread-based approaches.

Implementation of a CNN-based retinomorphic model on a high performance reconfigurable computer

The complexity of hardware design methodologies represents a significant difficulty for non-hardware focused scientists working on accelerating the simulation of complex bio-inspired applications. An emerging generation of electronic system level (ESL) design tools is been developed, which allow software–hardware codesign and partitioning of complex algorithms from high level language (HLL) descriptions. These tools, together with high performance reconfigurable computer (HPRC) systems consisting of standard microprocessors coupled with application specific FPGA chips, provide a new approach for rapid emulation and acceleration of highly parallelizable algorithms. In this article CoDeveloper, and ESL IDE from Impulse Accelerated Technologies, are analyzed. A model for the first synapse of the retina, based on a discrete-time sequential CNN architecture suitable for FPGA implementation proposed by the authors in a previous paper, is implemented using CoDeveloper tools and the DS1002 HPRC platform from DRC Computers. Results showed that, with a minimum development time, a 10×acceleration, when compared to the software emulation, can be obtained.

Lessons and Experiences with High-Level Synthesis

Electronic system level (ESL) design has attracted considerable attention in the past few years, and high level synthesis is a significant component of ESL design. Despite advances in HLS algorithms, the RTL remains the dominant specification and synthesis level. This article is a designer's perspective on the benefits and challenges of using commercially available HLS tools. They discuss their impact on four criteria: design goals, verification closure, eco handling, and productivity gains.

Guest Editors' Introduction: Raising the Abstraction Level of Hardware Design

Design complexity is continually rising with the higher levels of integration implied by Moore's law. Functional complexity increases as more computation is added to SoCs and as more-complex applications are developed. Additional complexity is introduced by the need to control power consumption and to tackle challenges with respect to physical timing closure and process variations. To manage this complexity requires automation, letting designers focus on high-level design decisions that have the most effect in the implementation's quality. A higher level of hardware design abstraction also enables an effective exploration of software and hardware architectures, making high-level synthesis a cornerstone of electronic system-level design. This special issue features nine articles that the authors believe will generate interest in the use of high-level synthesis and its further development.

SystemCoDesigner—an automatic ESL synthesis approach by design space exploration and behavioral synthesis for streaming applications

With increasing design complexity, the gap from ESL (Electronic System Level) design to RTL synthesis becomes more and more crucial to many industrial projects. Although several behavioral synthesis tools exist to automatically generate synthesizable RTL code from C/C++/SystemC-based input descriptions and software generation for embedded processors is automated as well, an efficient ESL synthesis methodology combining both is still missing. This article presents SystemCoDesigner, a novel SystemC-based ESL tool to automatically optimize a hardware/software SoC (System on Chip) implementation with respect to several objectives. Starting from a SystemC behavioral model, SystemCoDesigner automatically extracts the mathematical model, performs a behavioral synthesis step, and explores the multiobjective design space using state-of-the-art multiobjective optimization algorithms. During design space exploration, a single design point is evaluated by simulating highly accurate performance models, which are automatically generated from the SystemC behavioral model and the behavioral synthesis results. Moreover, SystemCoDesigner permits the automatic generation of bit streams for FPGA targets from any previously optimized SoC implementation. Thus SystemCoDesigner is the first fully automated ESL synthesis tool providing a correct-by-construction generation of hardware/software SoC implementations. As a case study, a model of a Motion-JPEG decoder was automatically optimized and implemented using SystemCoDesigner. Several synthesized SoC variants based on this model show different tradeoffs between required hardware costs and achieved system throughput, ranging from software-only solutions to pure hardware implementations that reach real-time performance for QCIF streams on a 50MHz FPGA.

The State of ESL Design [Roundtable

This is the first of two roundtables on electronic system-level design in this issue of IEEE Design & Test. ESL design and tools have been present in the design landscape for many years. Significant ESL innovations are now part of most advanced design methodologies, spanning the domains of modeling, simulation, and synthesis. Techniques such as transaction-level modeling, automatic interconnection generation, behavioral synthesis, automatic instruction-set customization, retargetable compilers, and many others are currently used in the design of multimillion-gate chips. Yet, ESL design still seems to struggle to live up to the promise of providing increased productivity and design quality. This roundtable examines these issues and attempts to provide a definite picture of where ESL design is today and where it might be in the next five to 10 years. The participants in this roundtable include well-known experts in ESL design from the user side, universities, and tool providers. IEEE Design & Test thanks the roundtable participants: moderator Reinaldo Bergamaschi (CadComponents), Luca Benini (University of Bologna), Krisztian Flautner (ARM UK), Wido Kruijtzer (NXP Semiconductors), Alberto Sangiovanni-Vincentelli (University of California, Berkeley), and Kazutoshi Wakabayashi (NEC Japan). D&T gratefully acknowledges the help of Roundtables Editor Bill Joyner (Semiconductor Research Corp.), who organized the event.

Advances in ESL Design

This is the second of two roundtables on electronic system-level (ESL) design, which recently has been seen as an advance in the EDA community--the latest attempt to improve designer productivity, shorten design time and cost, and improve design quality. Of course, "ESL" means different things to different people, and the notion varies even geographically--for example, between the US and Europe. The goal of this roundtable is to identify expectations and any meaningful advances associated with the notion of ESL design. What are the promising developments in the area? Which problems are relevant, and which are not? IEEE Design & Test thanks the roundtable participants: moderator Rajesh Gupta (University of California, San Diego), Arvind (Massachusetts Institute of Technology), Gerard Berry (Esterel Technologies), and Forrest Brewer (University of California, Santa Barbara). D&T gratefully acknowledges the help of Roundtables Editor Bill Joyner (Semiconductor Research Corp.), who organized the event.

Design and test for reliability and efficiency

This issue features two roundtables on electronic system-level (ESL) design, which has recently found its way into the mainstream EDA market. Composing system chips from basic building blocks is becoming increasingly more challenging as the number of devices and the number of physical effects impacting design quality increase. ESL design promises to be an effective high-level design methodology for achieving predictable functionality and performance while dealing with increased uncertainty and diversity in the underlying implementation fabrics. This issue of D&T also includes several general-interest articles that address various design, test, and reliability issues.

A cooperative universal data model platform for the data-centric electronic system-level design

The rapidly increasing complexity of integrated circuit design is evolving to a more data-centric design scenario that supports sharing of design information. This paper presents the universal data model platform (UDMP) which introduce the data-centric design revolution into the electronic system-level (ESL) design to support better cooperation of design individuals. UDMP provides (1) a set of universal data models to help both university researches and industry, and (2) an application programming interface (API) based mechanism for data exchanging to eliminate the inefficiency of traditional low-bandwidth formatted files. Thereby the cooperative work of ESL design and the efficiency of design iteration can be improved. As primary experiments, we apply the concepts of UDMP to two case studies. The heterogeneous graph modeling demonstrates how UDMP unifies the similar graph models in a flexible way, and the simplification of an interface synthesis flow which consists three individual algorithms obtains a running time reduction by about 10% for selected designs.

The ODYSSEY approach to early simulation-based equivalence checking at ESL level using automatically generated executable transaction-level model

Design technology is expected to rise to electronic system-level (ESL). This necessitates new techniques and tools for synthesizing ESL designs and for verifying them before and after ESL synthesis. A promising verification strategy for future very complex designs is to initially verify the design at the highest level of abstraction, and then check the equivalence of the lower level automatically generated models against that initial golden model. We present one such approach to simulation-based functional verification implemented in our ESL design methodology called ODYSSEY. Our ESL synthesis tool generates a transaction-level model (TLM) at TLM level 2 (i.e., design with partial timing) that corresponds to the input ESL design (which is at TLM level 3; i.e., sole functionality without timing). Both the ESL design and its generated TLM model can be simulated on a host machine with corresponding input stimuli to establish their functional equivalence. The TLM is in SystemC, and hence executable, and also models both hardware and software components in C++ to achieve higher simulation speed. We introduce an implementation of a TLM level 2 model that is tailored to our ESL design methodology and apply our approach to a number of benchmarks to evaluate the TLM simulation performance. Experimental results show that the approach suits early validation of the ESL synthesis process since its simulation performance is more than 4 orders of magnitude higher than simulations at lower levels and it is generated early in the design cycle. Also the co-simulation overhead – compared to simulating the original ESL design in C++ – depends on the partitioning quality in terms of communication to computation ratio.

Pre-synthesis resource generation and estimation for transport-triggered architecture (TTA)-like architecture

Electronic system level (ESL) design is widely adopted in today’s embedded systems development projects to cope with increasing system complexity and shrinking time-to-market. Even though functional verification can be performed at the system level and early design stage efficiently, it is still difficult to perform accurate hardware resource estimation. In this paper, we consider the problem of mapping an input high-level algorithm in C into hardware implementation based on the transport-triggered architecture (TTA)-like architecture, and present effective techniques for predicting architectural-level parameters and gate-level resource consumption without going through the lengthy hardware synthesis process in order to facilitate rapid design space exploration. We use some common DSP algorithms and a complete industry GPS application to show that our resource estimation results match the actual results from hardware synthesis very well, and they can be used in a feedback loop to optimize the input algorithm specification in C, e.g., the total gate count of the GPS application is reduced by 25% compared to the original input algorithm specification. In addition, the simulation results of the generated hardware descriptions in Verilog also show good agreement with the execution results of the original GPS program in C.

Enabling heterogeneous cycle-based and event-driven simulation in a design flow integrated using the SPIRIT consortium specifications

The practical application of electronic system-level (ESL) design has been a key challenge of transaction-level modeling (TLM) methodologies in the past few years. While the benefits of ESL are well known, making the investment pay-off has required two key factors to be resolved: the simulation speed of the virtual platform model has to be fast enough to enable software design, and the flow from ESL design to implementation has to be seamless. We introduce two themes to address these issues: cycle-based simulation and a multi-vendor design-flow integrated using the IP-XACTTM specifications from The SPIRIT Consortium. Through experimentation with the ARM RealView® SoC Designer flow, and the Synopsys coreAssembler tool and Galaxy suite of tools, we show that competent solutions to both of these adoption issues exist in the industry today.

The way to ESL

Electronic system level design promises faster development for complex system-on-chip designs. But getting there does not necessarily involve a straight path.

A high-level requirements engineering methodology for electronic system-level design

Current electronic systems’ complexity severely limits their validation. Even if development frameworks keep improving and are heavily supported by the industry, methods for hardware/software electronic systems co-design are reaching a major crisis. Although the community is heading towards higher abstraction levels, requirements remain out of the validation scope. We therefore present a requirements engineering methodology that intersects formal, linguistic, and scenario views. Modeling consists in abstracting functionalities’ behaviours in terms of actions, expressed in a semi-formal structured language, later automatically translated in a pure formal notation. Such a mix makes the language accessible to designers and permits automation. Validation is then performed using consistency rules. Finally, an elicitation of missing functionalities is achieved using Boolean algebra.

A Component-Based Design Environment for ESL Design

In this article, we present Gezel, a component-based, electronic system-level (ESL) design environment for heterogeneous designs. Gezel consists of a simple but extendable hardware description language (HDL) and an extensible simulation-and-refinement kernel. Our approach is to create a system by designing, integrating, and programming a set of programmable components. These components can be processor models or hard ware simulation kernels. Using Gezel, designers can clearly distinguish between component design, plat form integration, and platform programming, thus separating the roles of component builder, platform builder, and platform user. Embedded applications have driven the development of this ESL design environment. To demonstrate the broad scope of our component-based approach, we discuss three applications that use our environment; all are from the field of embedded security

The New World of ESL Design

This issue of IEEE Design & Test discusses some of the challenges of electronic system-level design and their corresponding solutions. In addition, a special section highlights the 2006 International Test Conference.

Target software generation: an approach for automatic mapping of SystemC specifications onto real-time operating systems

In this paper we present a new approach for automated target code generation for given real-time operating systems out of SystemC to support platform independent software development. Since SystemC becomes the most important language in electronic system level design, the support of a seamless design flow becomes an important task. During the system design process, SystemC is used to develop a "Golden Reference Model" that provides a well-suited platform for specification, simulation, and verification of embedded systems. Based on the "Golden Reference Model," an important task of the design process is to map applications, that have been described either in C++ or directly in SystemC, to the specific real-time operating system which is running at the target processor. Since a manual mapping approach is time-consuming and error-prone, the mapping process should be performed automatically. This paper presents a new method for automated generation of code for a specified operating system just by using an abstract XML representation of the RTOS API.